diff options
| author | Jes Klinke <jbk@google.com> | 2020-07-31 09:48:35 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-08-11 20:54:34 +0000 |
| commit | 739c50340431f34a8e4fbc0736ebb11e161fdf0f (patch) | |
| tree | b137b8d3fa20b787db3b59af8bf1b9a9a2ed576e /src/soc/intel/tigerlake/chip.c | |
| parent | 89ed7900287f3f38134aead3647eb153787604d1 (diff) | |
soc/intel/common/block/gspi: Recalculate BAR after resource allocation
The base address of the memory mapped I/O registers should not
be cached across resource allocation. This CL will evict the cached
value upon exiting the BS_DEV_RESOURCES stage.
Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44084
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.c')
0 files changed, 0 insertions, 0 deletions