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authorli feng <li1.feng@intel.com>2020-03-12 16:09:53 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-16 14:46:31 +0000
commit2cf9d3883cc09aa2410135b87d715f47608ae38d (patch)
treeb7aff1e00851ff70f058ecdb316ceb074c2c7b88 /src/soc/intel/tigerlake/chip.c
parentb159d443dd6e2bd977d30b3cb5db86b38430c1ea (diff)
soc/intel/tigerlake: Support ISH
Add ACPI Object for ISH SSDT Enable/disable ISH based on devicetree BRANCH=none BUG=b:145946347 TEST=boot to OS with TGL RVP UP3 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.c')
-rw-r--r--src/soc/intel/tigerlake/chip.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index 6f6e153ca6..dc36da34c4 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -71,6 +71,7 @@ const char *soc_acpi_name(const struct device *dev)
switch (dev->path.pci.devfn) {
case SA_DEVFN_ROOT: return "MCHC";
+ case PCH_DEVFN_ISH: return "ISHB";
case PCH_DEVFN_XHCI: return "XHCI";
case PCH_DEVFN_I2C0: return "I2C0";
case PCH_DEVFN_I2C1: return "I2C1";