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authorDuncan Laurie <dlaurie@google.com>2020-10-27 10:29:16 -0700
committerDuncan Laurie <dlaurie@chromium.org>2020-10-30 18:34:30 +0000
commit2e9315c4c666f7c49a90298723ec043f79371602 (patch)
tree233056ebbf1a77adc23ea3a97edd08f847abc84a /src/soc/intel/tigerlake/chip.c
parent0f5a17e98092dd6f340582ede5d481e53f90a06c (diff)
soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases
Enable the USB4 XHCI driver and remove the ACPI name entry from the SOC level function. Define aliases for the USB2/3 ports on north and south XHCI devices in chipset.cb so they can be referenced in the mainboard devicetree. BUG=b:151731851 TEST=define usb ports by reference in volteer devicetree and ensure they get properties added in SSDT for both north and south XHCI device. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I724ca874d3a3f6a2b43a700b0b10f77f25c53ee0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.c')
-rw-r--r--src/soc/intel/tigerlake/chip.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index 46c043fce9..62201a2f4f 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -66,7 +66,6 @@ const char *soc_acpi_name(const struct device *dev)
switch (dev->path.pci.devfn) {
case SA_DEVFN_ROOT: return "MCHC";
- case SA_DEVFN_TCSS_XHCI: return "TXHC";
case SA_DEVFN_TCSS_XDCI: return "TXDC";
case SA_DEVFN_TBT0: return "TRP0";
case SA_DEVFN_TBT1: return "TRP1";