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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 09:39:22 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-03 12:20:03 +0000 |
| commit | d8717197ae50dc9f68fbbde2f331d19b1d737351 (patch) | |
| tree | 513c11016877da092127c97ac4b5deafea15dbb6 /src/soc/intel/tigerlake/bootblock | |
| parent | 06897d1b1a7cc0af355c90cb317a8ad8210ea413 (diff) | |
soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I78f091e0d3d17fcfc60cd54721b34d143cbe2d86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/tigerlake/bootblock')
0 files changed, 0 insertions, 0 deletions