diff options
| author | Alexey Buyanov <alexey.buyanov@intel.com> | 2020-07-28 19:59:45 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-26 07:36:21 +0000 |
| commit | 12016969c50a34b7385ca435554be9670d031ea4 (patch) | |
| tree | 1295e67db8b3aa2f17593b03a1000ec786c78e97 /src/soc/intel/tigerlake/bootblock | |
| parent | 85a44639768e8365ba5e34e6752c7481534797b9 (diff) | |
soc/intel/tigerlake: Rename pch_init() code
Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.
TEST=successfully built and booted TGLRVP
Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com>
Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/bootblock')
| -rw-r--r-- | src/soc/intel/tigerlake/bootblock/bootblock.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/bootblock/pch.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index e7d97c50bf..96e6268f74 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -25,7 +25,7 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { report_platform_info(); - pch_init(); + bootblock_pch_init(); /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 63beeaa601..18ca5e51af 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -141,7 +141,7 @@ void pch_early_iorange_init(void) pch_enable_lpc(); } -void pch_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, |