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authorJeremy Soller <jeremy@system76.com>2021-08-12 10:49:58 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-08-24 14:48:50 +0000
commit83d795c45b602ed1736e80871b2bd5cd2ccf7490 (patch)
tree21a0c671ff0b6e7d922d7ffd26607715aed978e2 /src/soc/intel/tigerlake/acpi
parent21d7c477a45cef879669d436003c5834d3078dae (diff)
soc/intel/tigerlake: Add PCIe root ports for PCH-H
Change-Id: I89e300adce2edeb9d9c2bba1782c212ee656a532 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/acpi')
-rw-r--r--src/soc/intel/tigerlake/acpi/pcie.asl162
1 files changed, 158 insertions, 4 deletions
diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl
index a19feb7168..8219c653a7 100644
--- a/src/soc/intel/tigerlake/acpi/pcie.asl
+++ b/src/soc/intel/tigerlake/acpi/pcie.asl
@@ -54,7 +54,11 @@ Method (IRQM, 1, Serialized) {
Switch (ToInteger (Arg0))
{
- Case (Package () { 1, 5, 9, 13 }) {
+ Case (Package () { 1, 5, 9, 13
+#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
+ , 17, 21
+#endif
+ }) {
If (PICM) {
Return (IQAA)
} Else {
@@ -62,7 +66,11 @@ Method (IRQM, 1, Serialized) {
}
}
- Case (Package () { 2, 6, 10, 14 }) {
+ Case (Package () { 2, 6, 10, 14
+#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
+ , 18, 22
+#endif
+ }) {
If (PICM) {
Return (IQBA)
} Else {
@@ -70,7 +78,11 @@ Method (IRQM, 1, Serialized) {
}
}
- Case (Package () { 3, 7, 11, 15 }) {
+ Case (Package () { 3, 7, 11, 15
+#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
+ , 19, 23
+#endif
+ }) {
If (PICM) {
Return (IQCA)
} Else {
@@ -78,7 +90,11 @@ Method (IRQM, 1, Serialized) {
}
}
- Case (Package () { 4, 8, 12, 16 }) {
+ Case (Package () { 4, 8, 12, 16
+#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
+ , 20, 24
+#endif
+ }) {
If (PICM) {
Return (IQDA)
} Else {
@@ -299,3 +315,141 @@ Device (RP12)
Return (IRQM (RPPN))
}
}
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
+Device (RP17)
+{
+ Name (_ADR, 0x001B0000)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP18)
+{
+ Name (_ADR, 0x001B0001)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP19)
+{
+ Name (_ADR, 0x001B0002)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP20)
+{
+ Name (_ADR, 0x001B0003)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP21)
+{
+ Name (_ADR, 0x001B0004)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP22)
+{
+ Name (_ADR, 0x001B0005)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP23)
+{
+ Name (_ADR, 0x001B0006)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+
+Device (RP24)
+{
+ Name (_ADR, 0x001B0007)
+
+ OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ , 24,
+ RPPN, 8, /* Root Port Number */
+ }
+
+ Method (_PRT)
+ {
+ Return (IRQM (RPPN))
+ }
+}
+#endif /* CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) */