soc/intel/tigerlake: Correct IRQ interrupt

Current Interrupt setting use 2nd parameters as device function number.
- Correct as interrupt pin number according to _PRT package format.
  {Address, pin, Source, Source index}
- Use irq number directly rather than irq definition as its number
is not for PCI device.
The issue found while enabling GBE and GBE interrupt is not working
without this change.

Reference
- ACPI spec 6.2.13 _PRT
- FSP reference code:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c
- BIOS reference code:
https://github.com/otcshare/CCG-TGL-Generic-Full/blob/master/
TigerLakeBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl

TEST=boot to OS with GBE enabled and check GBE interrupt

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8084b30c668c155ebabbee90b5f70054813b328e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41153
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 121 insertions, 115 deletions

diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
index 536c75a950..6f5f4bc3fd 100644
--- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl
+++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
@@ -1,146 +1,152 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <soc/irq.h>
-
 Name (PICP, Package () {
-	/* D31:HDA, SMBUS, TraceHUB */
-	Package(){0x001FFFFF, 3, 0, HDA_IRQ },
-	Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
-	Package(){0x001FFFFF, 6, 0, GBE_IRQ },
-	Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
-	/* D30: UART0, UART1, SPI0, SPI1 */
-	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
-	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
-	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
-	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
-	/* D29: RP9 ~ RP12 */
-	Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
-	Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
-	Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
-	Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
-	/* D28: RP1 ~ RP8 */
-	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
-	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
-	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
-	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
-	Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
-	Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
-	Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
-	Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
-	/* D25: I2C4, I2C5, UART2 */
-	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
-	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
-	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
-	/* D23: SATA */
-	Package(){0x0017FFFF, 0, 0, SATA_IRQ },
-	/* D22: CSME */
-	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
-	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
-	Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
-	Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
-	/* D21: I2C0 ~ I2C3 */
-	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
-	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
-	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
-	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
-	/* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
-	Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
-	Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
-	Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
-	/* D19: SPI3 */
-	Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
-	/* D18: ISH, SPI2 */
-	Package(){0x0012FFFF, 0, 0, ISH_IRQ },
-	Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
-	/* D16: TCH0, TCH1 */
-	Package(){0x0010FFFF, 6, 0, THC0_IRQ },
-	Package(){0x0010FFFF, 7, 0, THC1_IRQ },
-	/* D13: xHCI, xDCI */
-	Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
-	Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
-	/* D8: GNA */
-	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
-	/* D7: TBT PCIe */
-	Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
-	Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
-	Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
-	Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
-	/* D6: PEG60 */
-	Package(){0x0006FFFF, 0, 0, PEG_IRQ },
-	/* D5: IPU Device */
-	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
-	/* D4:  Thermal Device */
-	Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
-	/* D2: IGFX */
-	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
+	/* D31 */
+	Package(){0x001FFFFF, 0, 0, 16 },
+	/* D30 */
+	Package(){0x001EFFFF, 0, 0, 16 },
+	Package(){0x001EFFFF, 1, 0, 17 },
+	Package(){0x001EFFFF, 2, 0, 36 },
+	Package(){0x001EFFFF, 3, 0, 37 },
+	/* D29 */
+	Package(){0x001DFFFF, 0, 0, 16 },
+	Package(){0x001DFFFF, 1, 0, 17 },
+	Package(){0x001DFFFF, 2, 0, 18 },
+	Package(){0x001DFFFF, 3, 0, 19 },
+	/* D28 */
+	Package(){0x001CFFFF, 0, 0, 16 },
+	Package(){0x001CFFFF, 1, 0, 17 },
+	Package(){0x001CFFFF, 2, 0, 18 },
+	Package(){0x001CFFFF, 3, 0, 19 },
+	/* D25 */
+	Package(){0x0019FFFF, 0, 0, 31 },
+	Package(){0x0019FFFF, 1, 0, 32 },
+	Package(){0x0019FFFF, 2, 0, 33 },
+	/* D23 */
+	Package(){0x0017FFFF, 0, 0, 16 },
+	/* D22 */
+	Package(){0x0016FFFF, 0, 0, 16 },
+	Package(){0x0016FFFF, 1, 0, 17 },
+	Package(){0x0016FFFF, 2, 0, 18 },
+	Package(){0x0016FFFF, 3, 0, 19 },
+	/* D21 */
+	Package(){0x0015FFFF, 0, 0, 27 },
+	Package(){0x0015FFFF, 1, 0, 40 },
+	Package(){0x0015FFFF, 2, 0, 29 },
+	Package(){0x0015FFFF, 3, 0, 30 },
+	/* D20 */
+	Package(){0x0014FFFF, 0, 0, 16 },
+	Package(){0x0014FFFF, 1, 0, 17 },
+	/* D19 */
+	Package(){0x0013FFFF, 0, 0, 43 },
+	Package(){0x0013FFFF, 1, 0, 24 },
+	Package(){0x0013FFFF, 2, 0, 25 },
+	Package(){0x0013FFFF, 3, 0, 38 },
+	/* D18 */
+	Package(){0x0012FFFF, 0, 0, 16 },
+	Package(){0x0012FFFF, 1, 0, 34 },
+	/* D17 */
+	Package(){0x0011FFFF, 0, 0, 35 },
+	Package(){0x0011FFFF, 1, 0, 20 },
+	Package(){0x0011FFFF, 2, 0, 21 },
+	Package(){0x0011FFFF, 3, 0, 42 },
+	/* D16 */
+	Package(){0x0010FFFF, 0, 0, 23 },
+	Package(){0x0010FFFF, 1, 0, 22 },
+	Package(){0x0010FFFF, 2, 0, 18 },
+	Package(){0x0010FFFF, 3, 0, 19 },
+	/* D13 */
+	Package(){0x000DFFFF, 0, 0, 16 },
+	Package(){0x000DFFFF, 1, 0, 17 },
+	/* D8 */
+	Package(){0x0008FFFF, 0, 0, 16 },
+	/* D7 */
+	Package(){0x0007FFFF, 0, 0, 16 },
+	Package(){0x0007FFFF, 1, 0, 17 },
+	Package(){0x0007FFFF, 2, 0, 18 },
+	Package(){0x0007FFFF, 3, 0, 19 },
+	/* D6 */
+	Package(){0x0006FFFF, 0, 0, 16 },
+	/* D5 */
+	Package(){0x0005FFFF, 0, 0, 16 },
+	/* D4 */
+	Package(){0x0004FFFF, 0, 0, 16 },
+	/* D2 */
+	Package(){0x0002FFFF, 0, 0, 16 },
 })
 
 Name (PICN, Package () {
-	/* D31:HDA, SMBUS, TraceHUB*/
-	Package () { 0x001FFFFF, 3, 0, 11 },
-	Package () { 0x001FFFFF, 4, 0, 11 },
-	Package () { 0x001FFFFF, 7, 0, 11 },
-	/* D30: UART0, UART1, SPI0, SPI1 */
-	Package () { 0x001EFFFF, 0, 0, 11 },
-	Package () { 0x001EFFFF, 1, 0, 10 },
-	Package () { 0x001EFFFF, 2, 0, 11 },
-	Package () { 0x001EFFFF, 3, 0, 11 },
-	/* D29: RP9 ~ RP12 */
-	Package () { 0x001DFFFF, 0, 0, 11 },
-	Package () { 0x001DFFFF, 1, 0, 10 },
-	Package () { 0x001DFFFF, 2, 0, 11 },
-	Package () { 0x001DFFFF, 3, 0, 11 },
-	/* D28: RP1 ~ RP8 */
-	Package () { 0x001CFFFF, 0, 0, 11 },
-	Package () { 0x001CFFFF, 1, 0, 10 },
-	Package () { 0x001CFFFF, 2, 0, 11 },
-	Package () { 0x001CFFFF, 3, 0, 11 },
-	Package () { 0x001CFFFF, 4, 0, 11 },
-	Package () { 0x001CFFFF, 5, 0, 10 },
-	Package () { 0x001CFFFF, 6, 0, 11 },
-	Package () { 0x001CFFFF, 7, 0, 11 },
-	/* D25: I2C4, I2C5, UART2 */
+	/* D31 */
+	Package(){0x001FFFFF, 0, 0, 11 },
+	/* D30 */
+	Package(){0x001EFFFF, 0, 0, 11 },
+	Package(){0x001EFFFF, 1, 0, 10 },
+	Package(){0x001EFFFF, 2, 0, 11 },
+	Package(){0x001EFFFF, 3, 0, 11 },
+	/* D29 */
+	Package(){0x001DFFFF, 0, 0, 11 },
+	Package(){0x001DFFFF, 1, 0, 10 },
+	Package(){0x001DFFFF, 2, 0, 11 },
+	Package(){0x001DFFFF, 3, 0, 11 },
+	/* D28 */
+	Package(){0x001CFFFF, 0, 0, 11 },
+	Package(){0x001CFFFF, 1, 0, 10 },
+	Package(){0x001CFFFF, 2, 0, 11 },
+	Package(){0x001CFFFF, 3, 0, 11 },
+	/* D25 */
 	Package(){0x0019FFFF, 0, 0, 11 },
 	Package(){0x0019FFFF, 1, 0, 10 },
 	Package(){0x0019FFFF, 2, 0, 11 },
-	/* D23: SATA */
-	Package () { 0x0017FFFF, 0, 0, 11 },
-	/* D22: CSME */
+	/* D23 */
+	Package(){0x0017FFFF, 0, 0, 11 },
+	/* D22 */
 	Package(){0x0016FFFF, 0, 0, 11 },
 	Package(){0x0016FFFF, 1, 0, 10 },
-	Package(){0x0016FFFF, 4, 0, 11 },
-	Package(){0x0016FFFF, 5, 0, 11 },
-	/* D21: I2C0 ~ I2C3 */
+	Package(){0x0016FFFF, 2, 0, 11 },
+	Package(){0x0016FFFF, 3, 0, 11 },
+	/* D21 */
 	Package(){0x0015FFFF, 0, 0, 11 },
 	Package(){0x0015FFFF, 1, 0, 10 },
 	Package(){0x0015FFFF, 2, 0, 11 },
 	Package(){0x0015FFFF, 3, 0, 11 },
-	/* D19: SPI3 */
+	/* D20 */
+	Package(){0x0014FFFF, 0, 0, 11 },
+	Package(){0x0014FFFF, 0, 0, 10 },
+	/* D19 */
 	Package(){0x0013FFFF, 0, 0, 11 },
-	/* D18: ISH, SPI2 */
+	Package(){0x0013FFFF, 1, 0, 10 },
+	Package(){0x0013FFFF, 2, 0, 11 },
+	Package(){0x0013FFFF, 3, 0, 11 },
+	/* D18 */
 	Package(){0x0012FFFF, 0, 0, 11 },
-	Package(){0x0012FFFF, 6, 0, 11 },,
-	/* D16: CNVI_BT, TCH0, TCH1 */
+	Package(){0x0012FFFF, 1, 0, 10 },,
+	/* D18 */
+	Package(){0x0011FFFF, 0, 0, 11 },
+	Package(){0x0011FFFF, 1, 0, 10 },
+	Package(){0x0011FFFF, 2, 0, 11 },
+	Package(){0x0011FFFF, 3, 0, 11 },
+	/* D16 */
+	Package(){0x0010FFFF, 0, 0, 11 },
+	Package(){0x0010FFFF, 1, 0, 10 },
 	Package(){0x0010FFFF, 2, 0, 11 },
-	Package(){0x0010FFFF, 6, 0, 11 },
-	Package(){0x0010FFFF, 7, 0, 10 },
-	/* D13: xHCI, xDCI */
+	Package(){0x0010FFFF, 3, 0, 11 },
+	/* D13 */
 	Package(){0x000DFFFF, 0, 0, 11 },
 	Package(){0x000DFFFF, 1, 0, 10 },
-	/* D8: GNA */
+	/* D8 */
 	Package(){0x0008FFFF, 0, 0, 11 },
-	/* D7: TBT PCIe */
+	/* D7 */
 	Package(){0x0007FFFF, 0, 0, 11 },
 	Package(){0x0007FFFF, 1, 0, 10 },
 	Package(){0x0007FFFF, 2, 0, 11 },
 	Package(){0x0007FFFF, 3, 0, 11 },
-	/* D6: PEG60 */
+	/* D6 */
 	Package(){0x0006FFFF, 0, 0, 11 },
-	/* D5: IPU Device */
+	/* D5 */
 	Package(){0x0005FFFF, 0, 0, 11 },
-	/* D4:  Thermal Device */
+	/* D4 */
 	Package(){0x0004FFFF, 0, 0, 11 },
-	/* D2: IGFX */
+	/* D2 */
 	Package(){0x0002FFFF, 0, 0, 11 },
 })