soc/intel/common/block/acpi: Factor out common gpio_op.asl

This patch moves gpio_op.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify all methods present inside
common gpio_op.asl like GRXS, GTXS etc. are still there.
2) Verify no ACPI error seen while running 'dmesg` from console.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I248f5e66994d2f3d6b0bd398347e7cf9ae7f2cc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

2 files changed, 1 insertions, 127 deletions

diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl
index b17abfe483..5a6e54a4a7 100644
--- a/src/soc/intel/tigerlake/acpi/gpio.asl
+++ b/src/soc/intel/tigerlake/acpi/gpio.asl
@@ -2,9 +2,9 @@
 #include <intelblocks/gpio.h>
 #include <soc/gpio_defs.h>
 #include <soc/intel/common/acpi/gpio.asl>
+#include <soc/intel/common/block/acpi/acpi/gpio_op.asl>
 #include <soc/irq.h>
 #include <soc/pcr_ids.h>
-#include "gpio_op.asl"
 
 Device (GPIO)
 {
diff --git a/src/soc/intel/tigerlake/acpi/gpio_op.asl b/src/soc/intel/tigerlake/acpi/gpio_op.asl
deleted file mode 100644
index ff12da4c10..0000000000
--- a/src/soc/intel/tigerlake/acpi/gpio_op.asl
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Get GPIO Value
- * Arg0 - GPIO Number
- */
-Method (GRXS, 1, Serialized)
-{
-	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
-	Field (PREG, AnyAcc, NoLock, Preserve)
-	{
-		VAL0, 32
-	}
-	Local0 = (PAD_CFG0_RX_STATE & VAL0) >> PAD_CFG0_RX_STATE_BIT
-
-	Return (Local0)
-}
-
-/*
- * Get GPIO Tx Value
- * Arg0 - GPIO Number
- */
-Method (GTXS, 1, Serialized)
-{
-	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
-	Field (PREG, AnyAcc, NoLock, Preserve)
-	{
-		VAL0, 32
-	}
-	Local0 = PAD_CFG0_TX_STATE & VAL0
-
-	Return (Local0)
-}
-
-/*
- * Set GPIO Tx Value
- * Arg0 - GPIO Number
- */
-Method (STXS, 1, Serialized)
-{
-	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
-	Field (PREG, AnyAcc, NoLock, Preserve)
-	{
-		VAL0, 32
-	}
-	VAL0 |= PAD_CFG0_TX_STATE
-}
-
-/*
- * Clear GPIO Tx Value
- * Arg0 - GPIO Number
- */
-Method (CTXS, 1, Serialized)
-{
-	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
-	Field (PREG, AnyAcc, NoLock, Preserve)
-	{
-		VAL0, 32
-	}
-	VAL0 &= ~PAD_CFG0_TX_STATE
-}
-
-/*
- * Set Pad mode
- * Arg0 - GPIO Number
- * Arg1 - Pad mode
- *     0 = GPIO control pad
- *     1 = Native Function 1
- *     2 = Native Function 2
- *     3 = Native Function 3
- */
-Method (GPMO, 2, Serialized)
-{
-	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
-	Field (PREG, AnyAcc, NoLock, Preserve)
-	{
-		VAL0, 32
-	}
-	Local0 = ~PAD_CFG0_MODE_MASK & VAL0
-	Arg1 = (Arg1 << PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK
-	VAL0 = Local0 | Arg1
-}
-
-/*
- * Enable/Disable Tx buffer
- * Arg0 - GPIO Number
- * Arg1 - TxBuffer state
- *     0 = Disable Tx Buffer
- *     1 = Enable Tx Buffer
- */
-Method (GTXE, 2, Serialized)
-{
-	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
-	Field (PREG, AnyAcc, NoLock, Preserve)
-	{
-		VAL0, 32
-	}
-
-	If (Arg1 == 1) {
-		VAL0 &= ~PAD_CFG0_TX_DISABLE
-	} ElseIf (Arg1 == 0){
-		VAL0 &= PAD_CFG0_TX_DISABLE
-	}
-}
-
-/*
- * Enable/Disable Rx buffer
- * Arg0 - GPIO Number
- * Arg1 - RxBuffer state
- *     0 = Disable Rx Buffer
- *     1 = Enable Rx Buffer
- */
-Method (GRXE, 2, Serialized)
-{
-	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
-	Field (PREG, AnyAcc, NoLock, Preserve)
-	{
-		VAL0, 32
-	}
-
-	If (Arg1 == 1) {
-		VAL0 &= ~PAD_CFG0_RX_DISABLE
-	} ElseIf (Arg1 == 0){
-		VAL0 |= PAD_CFG0_RX_DISABLE
-	}
-}