soc/intel/tigerlake: Add Jasper lake GPIO support

Add gpio definition for Jasper Lake gpio controller.

Also created a separate file for JSL and TGL gpio keeping common asl file.
gpio_soc_defs.h must pass correct information/macro values to asl file
for code to work.

GPIO controller includes 4 gpio community and 10 groups. Patch adds
definition for all gpio within community and groups

Updated IRQ mapping for all gpios

TEST=Check if jslrvp and tglrvp code is compiling

Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

2 files changed, 159 insertions, 76 deletions

diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl
index f6cccfb801..0378b52be3 100644
--- a/src/soc/intel/tigerlake/acpi/gpio.asl
+++ b/src/soc/intel/tigerlake/acpi/gpio.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2020 Intel Corp.
+ * Copyright 2020 The coreboot project Authors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,10 +15,12 @@
 #include <soc/gpio_defs.h>
 #include <soc/irq.h>
 #include <soc/pcr_ids.h>
+#include <intelblocks/gpio.h>
+#include "gpio_op.asl"
 
 Device (GCM0)
 {
-	Name (_HID, "INT34C5")
+	Name (_HID, CROS_GPIO_NAME)
 	Name (_UID, 0)
 	Name (_DDN, "GPIO Controller Community 0")
 
@@ -42,7 +44,7 @@ Device (GCM0)
 
 Device (GCM1)
 {
-	Name (_HID, "INT34C5")
+	Name (_HID, CROS_GPIO_NAME)
 	Name (_UID, 1)
 	Name (_DDN, "GPIO Controller Community 1")
 
@@ -66,7 +68,7 @@ Device (GCM1)
 
 Device (GCM4)
 {
-	Name (_HID, "INT34C5")
+	Name (_HID, CROS_GPIO_NAME)
 	Name (_UID, 4)
 	Name (_DDN, "GPIO Controller Community 4")
 
@@ -90,7 +92,7 @@ Device (GCM4)
 
 Device (GCM5)
 {
-	Name (_HID, "INT34C5")
+	Name (_HID, CROS_GPIO_NAME)
 	Name (_UID, 5)
 	Name (_DDN, "GPIO Controller Community 5")
 
@@ -119,95 +121,36 @@ Device (GCM5)
 Method (GADD, 1, NotSerialized)
 {
 	/* GPIO Community 0 */
-	If (Arg0 >= GPP_B0 && Arg0 <= GPP_A24)
+	If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END)
 	{
 		Local0 = PID_GPIOCOM0
-		Local1 = Arg0 - GPP_B0
+		Local1 = Arg0 - GPIO_COM0_START
 	}
 	/* GPIO Community 1 */
-	If (Arg0 >= GPP_S0 && Arg0 <= vI2S2_RXD)
+	If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END)
 	{
 		Local0 = PID_GPIOCOM1
-		Local1 = Arg0 - GPP_S0
+		Local1 = Arg0 - GPIO_COM1_START
 	}
 	/* GPIO Community 2 */
-	If (Arg0 >= GPD0 && Arg0 <= GPD_DRAM_RESETB)
+	If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END)
 	{
 		Local0 = PID_GPIOCOM2
-		Local1 = Arg0 - GPD0
+		Local1 = Arg0 - GPIO_COM2_START
 	}
 	/* GPIO Community 4 */
-	If (Arg0 >= GPP_C0 && Arg0 <= GPP_DBG_PMODE)
+	If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END)
 	{
 		Local0 = PID_GPIOCOM4
-		Local1 = Arg0 - GPP_C0
+		Local1 = Arg0 - GPIO_COM4_START
 	}
-	/* GPIO Community 5 */
-	If (Arg0 >= GPP_R0 && Arg0 <= GPP_CLK_LOOPBK)
+	/* GPIO Community 05*/
+	If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END)
 	{
 		Local0 = PID_GPIOCOM5
-		Local1 = Arg0 - GPP_R0
+		Local1 = Arg0 - GPIO_COM5_START
 	}
+
 	Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
 	Return (Local2)
 }
-
-/*
- * Get GPIO Value
- * Arg0 - GPIO Number
- */
-Method (GRXS, 1, Serialized)
-{
-	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
-	Field (PREG, AnyAcc, NoLock, Preserve)
-	{
-		VAL0, 32
-	}
-	Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT)
-
-	Return (Local0)
-}
-
-/*
- * Get GPIO Tx Value
- * Arg0 - GPIO Number
- */
-Method (GTXS, 1, Serialized)
-{
-	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
-	Field (PREG, AnyAcc, NoLock, Preserve)
-	{
-		VAL0, 32
-	}
-	Local0 = GPIOTXSTATE_MASK & VAL0
-
-	Return (Local0)
-}
-
-/*
- * Set GPIO Tx Value
- * Arg0 - GPIO Number
- */
-Method (STXS, 1, Serialized)
-{
-	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
-	Field (PREG, AnyAcc, NoLock, Preserve)
-	{
-		VAL0, 32
-	}
-	VAL0 |= GPIOTXSTATE_MASK
-}
-
-/*
- * Clear GPIO Tx Value
- * Arg0 - GPIO Number
- */
-Method (CTXS, 1, Serialized)
-{
-	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
-	Field (PREG, AnyAcc, NoLock, Preserve)
-	{
-		VAL0, 32
-	}
-	VAL0 &= ~GPIOTXSTATE_MASK
-}
diff --git a/src/soc/intel/tigerlake/acpi/gpio_op.asl b/src/soc/intel/tigerlake/acpi/gpio_op.asl
new file mode 100644
index 0000000000..a16ebf753d
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/gpio_op.asl
@@ -0,0 +1,140 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Get GPIO Value
+ * Arg0 - GPIO Number
+ */
+Method (GRXS, 1, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+	And (PAD_CFG0_RX_STATE, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0)
+
+	Return (Local0)
+}
+
+/*
+ * Get GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (GTXS, 1, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+	And (PAD_CFG0_TX_STATE, VAL0, Local0)
+
+	Return (Local0)
+}
+
+/*
+ * Set GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (STXS, 1, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+	Or (PAD_CFG0_TX_STATE, VAL0, VAL0)
+}
+
+/*
+ * Clear GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (CTXS, 1, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+	And (Not (PAD_CFG0_TX_STATE), VAL0, VAL0)
+}
+
+/*
+ * Set Pad mode
+ * Arg0 - GPIO Number
+ * Arg1 - Pad mode
+ *     0 = GPIO control pad
+ *     1 = Native Function 1
+ *     2 = Native Function 2
+ *     3 = Native Function 3
+ */
+Method (GPMO, 2, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+	Store (VAL0, Local0)
+	And (Not (PAD_CFG0_MODE_MASK), Local0, Local0)
+	And (ShiftLeft (Arg1, PAD_CFG0_MODE_SHIFT, Arg1), PAD_CFG0_MODE_MASK, Arg1)
+	Or (Local0, Arg1, VAL0)
+}
+
+/*
+ * Enable/Disable Tx buffer
+ * Arg0 - GPIO Number
+ * Arg1 - TxBuffer state
+ *     0 = Disable Tx Buffer
+ *     1 = Enable Tx Buffer
+ */
+Method (GTXE, 2, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+
+	If (LEqual (Arg1, 1)) {
+		And (Not (PAD_CFG0_TX_DISABLE), VAL0, VAL0)
+	} ElseIf (LEqual (Arg1, 0)){
+		Or (PAD_CFG0_TX_DISABLE, VAL0, VAL0)
+	}
+}
+
+/*
+ * Enable/Disable Rx buffer
+ * Arg0 - GPIO Number
+ * Arg1 - RxBuffer state
+ *     0 = Disable Rx Buffer
+ *     1 = Enable Rx Buffer
+ */
+Method (GRXE, 2, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+
+	If (LEqual (Arg1, 1)) {
+		And (Not (PAD_CFG0_RX_DISABLE), VAL0, VAL0)
+	} ElseIf (LEqual (Arg1, 0)){
+		Or (PAD_CFG0_RX_DISABLE, VAL0, VAL0)
+	}
+}