diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-02-13 22:07:00 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-02-15 04:10:46 +0000 |
| commit | 0e61a53b06bf0f1f0eba7a85e0a19fec97375717 (patch) | |
| tree | a6f05be9364b2944eedee7a256cde7b221f4b63b /src/soc/intel/tigerlake/acpi/xhci_tgl.asl | |
| parent | 77eaecf06b238157decfe19fea02eadfa71a9436 (diff) | |
soc/tigerlake: Update xhci ACPI files for JSP
ACPI files for xhci in JSL is different from TGL. Hence, renaming
xhci.asl to xhci_tgl.asl and adding a new file xhci_jsl.asl for JSL.
Also, allowing xhci.asl to choose the correct file based on the SoC
selected.
BUG=None
BRANCH=None
TEST=Compilation for JasperLake board is working
Change-Id: Ia8e88e02989ff80d7cd1f28941e005cb0d842fcb
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/acpi/xhci_tgl.asl')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/xhci_tgl.asl | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/acpi/xhci_tgl.asl b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl new file mode 100644 index 0000000000..312cc5a88e --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpe.h> + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Method (_PS0, 0, Serialized) + { + + } + + Method (_PS3, 0, Serialized) + { + + } + + /* Root Hub for Tigerlake-LP PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + + /* USB3 */ + Device (SS01) { Name (_ADR, 13) } + Device (SS02) { Name (_ADR, 14) } + Device (SS03) { Name (_ADR, 15) } + Device (SS04) { Name (_ADR, 16) } + } +} |