diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2019-12-16 23:23:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-18 11:19:03 +0000 |
| commit | 954a5b50ad9d6ee31f0f0d7abe6badf412cbe9cc (patch) | |
| tree | 03e6b598cef6e8d739269ae90d21c6c7b661b5d2 /src/soc/intel/tigerlake/acpi/xhci.asl | |
| parent | 69855f2e609483b2cbe4aebf7fa6ca1dde0bfc30 (diff) | |
soc/intel/tigerlake: Update ACPI files
Add and update ACPI files for Tiger Lake SoC
Use ASL2.0 code syntax for new acpi(camera_clock_ctl.asl)
Reference
PCH EDS#576591 vol1 rev1.2
PCH EDS#575857 vol2 rev1.0
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ib82156830273c2937f5f02713ed7dd27da41c857
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37781
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/acpi/xhci.asl')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/xhci.asl | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/tigerlake/acpi/xhci.asl b/src/soc/intel/tigerlake/acpi/xhci.asl index 8268bd516f..312cc5a88e 100644 --- a/src/soc/intel/tigerlake/acpi/xhci.asl +++ b/src/soc/intel/tigerlake/acpi/xhci.asl @@ -53,19 +53,11 @@ Device (XHCI) Device (HS08) { Name (_ADR, 8) } Device (HS09) { Name (_ADR, 9) } Device (HS10) { Name (_ADR, 10) } - Device (HS11) { Name (_ADR, 11) } - Device (HS12) { Name (_ADR, 12) } - - /* USBr */ - Device (USR1) { Name (_ADR, 11) } - Device (USR2) { Name (_ADR, 12) } /* USB3 */ Device (SS01) { Name (_ADR, 13) } Device (SS02) { Name (_ADR, 14) } Device (SS03) { Name (_ADR, 15) } Device (SS04) { Name (_ADR, 16) } - Device (SS05) { Name (_ADR, 17) } - Device (SS06) { Name (_ADR, 18) } } } |