soc/intel/tigerlake: Configure TCSS power management

Add Type-C subsystem power management support for RTD3.

BUG=b:140290596
TEST=Include "tcss.asl" in platform "dsdt.asl" for coreboot build
with the firmware CM. Added acpi debug and booted to kernel. Probed
devices PM_STATE transition from D0 to D3 entry/exit while system at S0.
TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3, offset:0xA4, PM_STATE:D3HT.
xhci:00:0d.0, offset:0x74, PM_STATE:D0D3.
dma:00:0d.2/00.0d.3, offset:0x84, PM_STATE:PMST.
Verified xhci/dma/pcie root ports power runtime_status to be suspended and suspended
time tick through /sys/bus/pci/devices/bus:device:func/power.

Change-Id: I127d3700ad426a44639ee93b4477be6638b42e1b
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

1 files changed, 138 insertions, 0 deletions

diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
new file mode 100644
index 0000000000..e78cc1d482
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+OperationRegion (XPRT, SystemMemory, BASE(_ADR), 0x100)
+Field (XPRT, ByteAcc, NoLock, Preserve)
+{
+	VDID,  32,
+	Offset(0x74),   /* 0x74, XHCI CFG Power Control And Status */
+	D0D3,  2,       /* 0x74 BIT[1:0] */
+	    ,  6,
+	PMEE,  1,       /* PME Enable */
+	    ,  6,
+	PMES,  1,       /* PME Status */
+}
+
+Method (_PS0, 0, Serialized)
+{
+	If (\_SB.PCI0.TXHC.PMEE == 1) {
+		/* Clear PME_EN of CPU xHCI */
+		\_SB.PCI0.TXHC.PMEE = 0
+	}
+}
+
+Method (_PS3, 0, Serialized)
+{
+	If (\_SB.PCI0.TXHC.PMEE == 0) {
+		/* Set PME_EN of CPU xHCI */
+		\_SB.PCI0.TXHC.PMEE = 1
+	}
+}
+
+Method (_S0W, 0x0, NotSerialized)
+{
+	Return (0x4)
+}
+
+/*
+ * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE
+ * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0.
+ */
+Name (SD3C, 0)
+
+Method (_PR0)
+{
+	Return (Package () { \_SB.PCI0.D3C })
+}
+
+Method (_PR3)
+{
+	Return (Package () { \_SB.PCI0.D3C })
+}
+
+/*
+ * XHCI controller _DSM method
+ */
+Method (_DSM, 4, serialized)
+{
+	Return (Buffer() { 0 })
+}
+
+/*
+ * _SXD and _SXW methods
+ */
+Method (_S3D, 0, NotSerialized)
+{
+	Return (3)
+}
+
+Method (_S4D, 0, NotSerialized)
+{
+	Return (3)
+}
+
+Method (_S3W, 0, NotSerialized)
+{
+	Return (3)
+}
+
+Method (_S4W, 0, NotSerialized)
+{
+	Return (3)
+}
+
+/*
+ * Power resource for wake
+ */
+Method (_PRW, 0)
+{
+	Return (Package() { 0x6D, 4 })
+}
+
+/*
+ * Device sleep wake
+ */
+Method (_DSW, 3)
+{
+	C2PM (Arg0, Arg1, Arg2, DCPM)
+	/* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */
+	SD3C = Arg1
+}
+
+/*
+ * xHCI Root Hub Device
+ */
+Device (RHUB)
+{
+	Name (_ADR, Zero)
+
+	/* High Speed Ports */
+	Device (HS01)
+	{
+		Name (_ADR, 0x01)
+	}
+
+	/* Super Speed Ports */
+	Device (SS01)
+	{
+		Name (_ADR, 0x02)
+	}
+
+	Device (SS02)
+	{
+		Name (_ADR, 0x03)
+	}
+
+	Device (SS03)
+	{
+		Name (_ADR, 0x04)
+	}
+
+	Device (SS04)
+	{
+		Name (_ADR, 0x05)
+	}
+}