diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-10 19:31:26 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-16 09:39:04 +0000 |
| commit | fce36e448dcb6346e270bcfa4ec97df09188808e (patch) | |
| tree | 750e4735d21787dd76cbfc61423596a42af2a4c4 /src/soc/intel/tigerlake/Kconfig | |
| parent | 11c6b8b53182c5c83095136712f3d38eb5c1dd6a (diff) | |
vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMIC
Always allocate RAMOOPS from CBMEM and drop the related
static variable CHROMEOS_RAMOOPS_RAM_START.
Change-Id: Icfcf2991cb78cc6e9becba14cac77a04d8ada56a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50608
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/Kconfig')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 3e080cce60..c6bb167c9f 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -191,9 +191,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL hex default 0x7fff -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - # Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection # in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. config TPM_CR50 |