diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2019-12-16 23:41:36 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-18 11:01:40 +0000 |
| commit | 2fd49721b17f9020c2b449aad778f011dae7bf46 (patch) | |
| tree | 046e62e13fa9d46542b725bae8e15657ce9e6616 /src/soc/intel/tigerlake/Kconfig | |
| parent | 92bd83979f8a7b855a78e9bea2d274d1a4f308b6 (diff) | |
soc/intel/tigerlake: Update chip files
Update chip files to include :
- Update chip.c based on TGL FSP
- Update chip.h based on TGL FSP
- Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update
- Update pmc_utils.c and JSL devicetree for build failure
Reference
PCH EDS#576591 vol1 rev1.2
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/Kconfig')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index f1ae8a82c9..9340f6980c 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -115,6 +115,11 @@ config MAX_ROOT_PORTS default 16 if SOC_INTEL_JASPERLAKE default 12 if SOC_INTEL_TIGERLAKE +config MAX_PCIE_CLOCKS + int + default 7 if SOC_INTEL_TIGERLAKE + default 16 if SOC_INTEL_JASPERLAKE + config SMM_TSEG_SIZE hex default 0x800000 |