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authorDuncan Laurie <dlaurie@google.com>2020-10-27 10:29:16 -0700
committerDuncan Laurie <dlaurie@chromium.org>2020-10-30 18:34:30 +0000
commit2e9315c4c666f7c49a90298723ec043f79371602 (patch)
tree233056ebbf1a77adc23ea3a97edd08f847abc84a /src/soc/intel/tigerlake/Kconfig
parent0f5a17e98092dd6f340582ede5d481e53f90a06c (diff)
soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases
Enable the USB4 XHCI driver and remove the ACPI name entry from the SOC level function. Define aliases for the USB2/3 ports on north and south XHCI devices in chipset.cb so they can be referenced in the mainboard devicetree. BUG=b:151731851 TEST=define usb ports by reference in volteer devicetree and ensure they get properties added in SSDT for both north and south XHCI device. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I724ca874d3a3f6a2b43a700b0b10f77f25c53ee0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/Kconfig')
-rw-r--r--src/soc/intel/tigerlake/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 2b5f0baeb1..9eb229e207 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION
+ select DRIVERS_USB_ACPI
select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP
select GENERIC_GPIO_LIB
@@ -50,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_USB4
select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
+ select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_CAR