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authorYuchi Chen <yuchi.chen@intel.com>2024-09-27 18:10:41 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-11-27 09:31:52 +0000
commit78fa36d0508fb94634f9c17a28186caab4c3f3f3 (patch)
treed7719ca4587cf3605f9a63053dac5fc3c9a9a5cd /src/soc/intel/snowridge/finalize.c
parentd2deb14fb00f71fca4897e44b4d61d8027d2bdf3 (diff)
soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
This change adds support for Intel Atom Processors P5300, P5700 product families (known as Snow Ridge NS and Snow Ridge NX). Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Tested-by: Vasiliy Khoruzhick <vasilykh@arista.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src/soc/intel/snowridge/finalize.c')
-rw-r--r--src/soc/intel/snowridge/finalize.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/snowridge/finalize.c b/src/soc/intel/snowridge/finalize.c
new file mode 100644
index 0000000000..476b2c1f3d
--- /dev/null
+++ b/src/soc/intel/snowridge/finalize.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <commonlib/console/post_codes.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+
+static void soc_finalize(void *unused)
+{
+ printk(BIOS_DEBUG, "Finalizing chipset.\n");
+
+ apm_control(APM_CNT_FINALIZE);
+
+ /* Indicate finalize step with post code */
+ post_code(POSTCODE_OS_BOOT);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);