soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

This change adds support for Intel Atom Processors P5300, P5700
product families (known as Snow Ridge NS and Snow Ridge NX).

Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Tested-by: Vasiliy Khoruzhick <vasilykh@arista.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>

13 files changed, 1182 insertions, 0 deletions

diff --git a/src/soc/intel/snowridge/common/fsp_hob.c b/src/soc/intel/snowridge/common/fsp_hob.c
new file mode 100644
index 0000000000..426e6c3cf9
--- /dev/null
+++ b/src/soc/intel/snowridge/common/fsp_hob.c
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/util.h>
+
+#include "fsp_hob.h"
+
+const guid_t fsp_hob_fia_override_status_guid = {
+	.b = {0xc1, 0x94, 0x8d, 0x61, 0xde, 0x0e, 0xe3, 0x4e, 0x98, 0x4F, 0xB2, 0x07, 0x6B,
+	      0x05, 0x50, 0xFB}
+};
+
+const guid_t fsp_hob_iio_uds_data_guid = {
+	.b = {0xbd, 0x74, 0x6b, 0x83, 0xf3, 0xc2, 0x28, 0x4d, 0xa3, 0xb8, 0x91, 0x33, 0x10,
+	      0x52, 0x52, 0x9b}
+};
+
+const guid_t fsp_hob_kti_cache_guid = {
+	.b = {0xd6, 0xd3, 0x45, 0xac, 0x6e, 0xa3, 0xa6, 0x43, 0xad, 0x17, 0x0a, 0x45, 0xbb,
+	      0x47, 0xbe, 0xd6}
+};
+
+const guid_t fsp_hob_smbios_memory_info_guid = {
+	.b = {0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, 0x88, 0xc3, 0xee, 0xe8, 0xc4,
+	      0x9e, 0xfb, 0x89}
+};
+
+static const void *fsp_hob_get(const guid_t *guid, size_t *hob_size)
+{
+	return fsp_find_extension_hob_by_guid(guid->b, hob_size);
+}
+
+const BL_IIO_UDS *fsp_hob_get_iio_uds_data(void)
+{
+	size_t unused;
+
+	return fsp_hob_get(&fsp_hob_iio_uds_data_guid, &unused);
+}
+
+const void *fsp_hob_get_kti_cache(size_t *hob_size)
+{
+	return fsp_hob_get(&fsp_hob_kti_cache_guid, hob_size);
+}
+
+const FSP_SMBIOS_MEMORY_INFO *fsp_hob_get_memory_info(void)
+{
+	size_t unused;
+
+	return fsp_hob_get(&fsp_hob_smbios_memory_info_guid, &unused);
+}
diff --git a/src/soc/intel/snowridge/common/fsp_hob.h b/src/soc/intel/snowridge/common/fsp_hob.h
new file mode 100644
index 0000000000..e5c96bdd27
--- /dev/null
+++ b/src/soc/intel/snowridge/common/fsp_hob.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_SNOWRIDGE_FSP_HOB_H_
+#define _SOC_SNOWRIDGE_FSP_HOB_H_
+
+#include <fsp/soc_binding.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <uuid.h>
+
+extern const guid_t fsp_hob_fia_override_status_guid;
+extern const guid_t fsp_hob_iio_uds_data_guid;
+extern const guid_t fsp_hob_kti_cache_guid;
+extern const guid_t fsp_hob_smbios_memory_info_guid;
+
+const BL_IIO_UDS *fsp_hob_get_iio_uds_data(void);
+const void *fsp_hob_get_kti_cache(size_t *hob_size);
+const FSP_SMBIOS_MEMORY_INFO *fsp_hob_get_memory_info(void);
+
+#endif // _SOC_SNOWRIDGE_FSP_HOB_H_
diff --git a/src/soc/intel/snowridge/common/gpio.c b/src/soc/intel/snowridge/common/gpio.c
new file mode 100644
index 0000000000..8bf5edf50e
--- /dev/null
+++ b/src/soc/intel/snowridge/common/gpio.c
@@ -0,0 +1,314 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/gpio.h>
+#include <soc/gpio_snr.h>
+#include <soc/pcr_ids.h>
+
+static const struct pad_group snr_community_west2_groups[] = {
+	INTEL_GPP(GPIO_WEST2_0, GPIO_WEST2_0, GPIO_WEST2_23),
+};
+
+static const struct pad_group snr_community_west3_groups[] = {
+	INTEL_GPP(GPIO_WEST3_0, GPIO_WEST3_0, GPIO_WEST3_23),
+};
+
+static const struct pad_group snr_community_west01_groups[] = {
+	INTEL_GPP(GPIO_WEST01_0, GPIO_WEST01_0, GPIO_WEST01_22),
+};
+
+static const struct pad_group snr_community_west5_groups[] = {
+	INTEL_GPP(GPIO_WEST5_0, GPIO_WEST5_0, GPIO_WEST5_18),
+};
+
+static const struct pad_group snr_community_westb_groups[] = {
+	INTEL_GPP(GPIO_WESTB_0, GPIO_WESTB_0, GPIO_WESTB_11),
+};
+
+static const struct pad_group snr_community_westd_peci_groups[] = {
+	INTEL_GPP(GPIO_WESTD_PECI_0, GPIO_WESTD_PECI_0, GPIO_WESTD_PECI_0),
+};
+
+static const struct pad_group snr_community_east2_groups[] = {
+	INTEL_GPP(GPIO_EAST2_0, GPIO_EAST2_0, GPIO_EAST2_23),
+};
+
+static const struct pad_group snr_community_east3_groups[] = {
+	INTEL_GPP(GPIO_EAST3_0, GPIO_EAST3_0, GPIO_EAST3_9),
+};
+
+static const struct pad_group snr_community_east0_groups[] = {
+	INTEL_GPP(GPIO_EAST0_0, GPIO_EAST0_0, GPIO_EAST0_22),
+};
+
+static const struct pad_group snr_community_emmc_groups[] = {
+	INTEL_GPP(GPIO_EMMC_0, GPIO_EMMC_0, GPIO_EMMC_10),
+};
+
+static const struct pad_community snr_gpio_communities[] = {
+	{
+		.name = "GPIO_WEST2",
+		.acpi_path = "\\_SB.GPO0",
+		.num_gpi_regs = GPIO_WEST2_GPI_STATUS_REGS,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.first_pad = GPIO_WEST2_0,
+		.last_pad = GPIO_WEST2_23,
+		.pad_own_reg_0 = GPIO_WEST2_PAD_OWN,
+		.host_own_reg_0 = GPIO_WEST2_HOSTSW_OWN,
+		.gpi_int_sts_reg_0 = GPIO_WEST2_GPI_IS,
+		.gpi_int_en_reg_0 = GPIO_WEST2_GPI_IE,
+		.gpi_smi_sts_reg_0 = GPIO_WEST2_SMI_STS,
+		.gpi_smi_en_reg_0 = GPIO_WEST2_SMI_EN,
+		.gpi_gpe_sts_reg_0 = GPIO_WEST2_GPI_GPE_STS,
+		.gpi_gpe_en_reg_0 = GPIO_WEST2_GPI_GPE_EN,
+		.gpi_nmi_sts_reg_0 = GPIO_WEST2_NMI_STS,
+		.gpi_nmi_en_reg_0 = GPIO_WEST2_NMI_EN,
+		.pad_cfg_base = GPIO_WEST2_PADCFG_OFFSET,
+		.pad_cfg_lock_offset = GPIO_WEST2_PADCFGLOCK,
+		.gpi_status_offset = 0,
+		.port = PID_GPIOCOM1,
+		.groups = snr_community_west2_groups,
+		.num_groups = ARRAY_SIZE(snr_community_west2_groups),
+	},
+	{
+		.name = "GPIO_WEST3",
+		.acpi_path = "\\_SB.GPO1",
+		.num_gpi_regs = GPIO_WEST3_GPI_STATUS_REGS,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.first_pad = GPIO_WEST3_0,
+		.last_pad = GPIO_WEST3_23,
+		.pad_own_reg_0 = GPIO_WEST3_PAD_OWN,
+		.host_own_reg_0 = GPIO_WEST3_HOSTSW_OWN,
+		.gpi_int_sts_reg_0 = GPIO_WEST3_GPI_IS,
+		.gpi_int_en_reg_0 = GPIO_WEST3_GPI_IE,
+		.gpi_smi_sts_reg_0 = GPIO_WEST3_SMI_STS,
+		.gpi_smi_en_reg_0 = GPIO_WEST3_SMI_EN,
+		.gpi_gpe_sts_reg_0 = GPIO_WEST3_GPI_GPE_STS,
+		.gpi_gpe_en_reg_0 = GPIO_WEST3_GPI_GPE_EN,
+		.gpi_nmi_sts_reg_0 = GPIO_WEST3_NMI_STS,
+		.gpi_nmi_en_reg_0 = GPIO_WEST3_NMI_EN,
+		.pad_cfg_base = GPIO_WEST3_PADCFG_OFFSET,
+		.pad_cfg_lock_offset = GPIO_WEST3_PADCFGLOCK,
+		.gpi_status_offset = GPIO_WEST2_GPI_STATUS_REGS,
+		.port = PID_GPIOCOM1,
+		.groups = snr_community_west3_groups,
+		.num_groups = ARRAY_SIZE(snr_community_west3_groups),
+	},
+	{
+		.name = "GPIO_WEST01",
+		.acpi_path = "\\_SB.GPO2",
+		.num_gpi_regs = GPIO_WEST01_GPI_STATUS_REGS,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.first_pad = GPIO_WEST01_0,
+		.last_pad = GPIO_WEST01_22,
+		.pad_own_reg_0 = GPIO_WEST01_PAD_OWN,
+		.host_own_reg_0 = GPIO_WEST01_HOSTSW_OWN,
+		.gpi_int_sts_reg_0 = GPIO_WEST01_GPI_IS,
+		.gpi_int_en_reg_0 = GPIO_WEST01_GPI_IE,
+		.gpi_smi_sts_reg_0 = GPIO_WEST01_SMI_STS,
+		.gpi_smi_en_reg_0 = GPIO_WEST01_SMI_EN,
+		.gpi_gpe_sts_reg_0 = GPIO_WEST01_GPI_GPE_STS,
+		.gpi_gpe_en_reg_0 = GPIO_WEST01_GPI_GPE_EN,
+		.gpi_nmi_sts_reg_0 = GPIO_WEST01_NMI_STS,
+		.gpi_nmi_en_reg_0 = GPIO_WEST01_NMI_EN,
+		.pad_cfg_base = GPIO_WEST01_PADCFG_OFFSET,
+		.pad_cfg_lock_offset = GPIO_WEST01_PADCFGLOCK,
+		.gpi_status_offset = GPIO_WEST2_GPI_STATUS_REGS + GPIO_WEST3_GPI_STATUS_REGS,
+		.port = PID_GPIOCOM1,
+		.groups = snr_community_west01_groups,
+		.num_groups = ARRAY_SIZE(snr_community_west01_groups),
+	},
+	{
+		.name = "GPIO_WEST5",
+		.acpi_path = "\\_SB.GPO3",
+		.num_gpi_regs = GPIO_WEST5_GPI_STATUS_REGS,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.first_pad = GPIO_WEST5_0,
+		.last_pad = GPIO_WEST5_18,
+		.pad_own_reg_0 = GPIO_WEST5_PAD_OWN,
+		.host_own_reg_0 = GPIO_WEST5_HOSTSW_OWN,
+		.gpi_int_sts_reg_0 = GPIO_WEST5_GPI_IS,
+		.gpi_int_en_reg_0 = GPIO_WEST5_GPI_IE,
+		.gpi_smi_sts_reg_0 = GPIO_WEST5_SMI_STS,
+		.gpi_smi_en_reg_0 = GPIO_WEST5_SMI_EN,
+		.gpi_gpe_sts_reg_0 = GPIO_WEST5_GPI_GPE_STS,
+		.gpi_gpe_en_reg_0 = GPIO_WEST5_GPI_GPE_EN,
+		.gpi_nmi_sts_reg_0 = GPIO_WEST5_NMI_STS,
+		.gpi_nmi_en_reg_0 = GPIO_WEST5_NMI_EN,
+		.pad_cfg_base = GPIO_WEST5_PADCFG_OFFSET,
+		.pad_cfg_lock_offset = GPIO_WEST5_PADCFGLOCK,
+		.gpi_status_offset = GPIO_WEST2_GPI_STATUS_REGS + GPIO_WEST3_GPI_STATUS_REGS +
+				     GPIO_WEST01_GPI_STATUS_REGS,
+		.port = PID_GPIOCOM1,
+		.groups = snr_community_west5_groups,
+		.num_groups = ARRAY_SIZE(snr_community_west5_groups),
+	},
+	{
+		.name = "GPIO_WESTB",
+		.acpi_path = "\\_SB.GPO4",
+		.num_gpi_regs = GPIO_WESTB_GPI_STATUS_REGS,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.first_pad = GPIO_WESTB_0,
+		.last_pad = GPIO_WESTB_11,
+		.pad_own_reg_0 = GPIO_WESTB_PAD_OWN,
+		.host_own_reg_0 = GPIO_WESTB_HOSTSW_OWN,
+		.gpi_int_sts_reg_0 = GPIO_WESTB_GPI_IS,
+		.gpi_int_en_reg_0 = GPIO_WESTB_GPI_IE,
+		.gpi_smi_sts_reg_0 = GPIO_WESTB_SMI_STS,
+		.gpi_smi_en_reg_0 = GPIO_WESTB_SMI_EN,
+		.gpi_gpe_sts_reg_0 = GPIO_WESTB_GPI_GPE_STS,
+		.gpi_gpe_en_reg_0 = GPIO_WESTB_GPI_GPE_EN,
+		.gpi_nmi_sts_reg_0 = GPIO_WESTB_NMI_STS,
+		.gpi_nmi_en_reg_0 = GPIO_WESTB_NMI_EN,
+		.pad_cfg_base = GPIO_WESTB_PADCFG_OFFSET,
+		.pad_cfg_lock_offset = GPIO_WESTB_PADCFGLOCK,
+		.gpi_status_offset = GPIO_WEST2_GPI_STATUS_REGS + GPIO_WEST3_GPI_STATUS_REGS +
+				     GPIO_WEST01_GPI_STATUS_REGS + GPIO_WEST5_GPI_STATUS_REGS,
+		.port = PID_GPIOCOM1,
+		.groups = snr_community_westb_groups,
+		.num_groups = ARRAY_SIZE(snr_community_westb_groups),
+	},
+	{
+		.name = "GPIO_WESTD_PECI",
+		.acpi_path = "\\_SB.GPO5",
+		.num_gpi_regs = GPIO_WESTD_PECI_GPI_STATUS_REGS,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.first_pad = GPIO_WESTD_PECI_0,
+		.last_pad = GPIO_WESTD_PECI_0,
+		.pad_own_reg_0 = GPIO_WESTD_PECI_PAD_OWN,
+		.host_own_reg_0 = GPIO_WESTD_PECI_HOSTSW_OWN,
+		.gpi_int_sts_reg_0 = GPIO_WESTD_PECI_GPI_IS,
+		.gpi_int_en_reg_0 = GPIO_WESTD_PECI_GPI_IE,
+		.gpi_smi_sts_reg_0 = GPIO_WESTD_PECI_SMI_STS,
+		.gpi_smi_en_reg_0 = GPIO_WESTD_PECI_SMI_EN,
+		.gpi_gpe_sts_reg_0 = GPIO_WESTD_PECI_GPI_GPE_STS,
+		.gpi_gpe_en_reg_0 = GPIO_WESTD_PECI_GPI_GPE_EN,
+		.gpi_nmi_sts_reg_0 = GPIO_WESTD_PECI_NMI_STS,
+		.gpi_nmi_en_reg_0 = GPIO_WESTD_PECI_NMI_EN,
+		.pad_cfg_base = GPIO_WESTD_PECI_PADCFG_OFFSET,
+		.pad_cfg_lock_offset = GPIO_WESTD_PECI_PADCFGLOCK,
+		.gpi_status_offset = GPIO_WEST2_GPI_STATUS_REGS + GPIO_WEST3_GPI_STATUS_REGS +
+				     GPIO_WEST01_GPI_STATUS_REGS + GPIO_WEST5_GPI_STATUS_REGS +
+				     GPIO_WESTB_GPI_STATUS_REGS,
+		.port = PID_GPIOCOM1,
+		.groups = snr_community_westd_peci_groups,
+		.num_groups = ARRAY_SIZE(snr_community_westd_peci_groups),
+	},
+	{
+		.name = "GPIO_EAST2",
+		.acpi_path = "\\_SB.GPO11",
+		.num_gpi_regs = GPIO_EAST2_GPI_STATUS_REGS,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.first_pad = GPIO_EAST2_0,
+		.last_pad = GPIO_EAST2_23,
+		.pad_own_reg_0 = GPIO_EAST2_PAD_OWN,
+		.host_own_reg_0 = GPIO_EAST2_HOSTSW_OWN,
+		.gpi_int_sts_reg_0 = GPIO_EAST2_GPI_IS,
+		.gpi_int_en_reg_0 = GPIO_EAST2_GPI_IE,
+		.gpi_smi_sts_reg_0 = GPIO_EAST2_SMI_STS,
+		.gpi_smi_en_reg_0 = GPIO_EAST2_SMI_EN,
+		.gpi_gpe_sts_reg_0 = GPIO_EAST2_GPI_GPE_STS,
+		.gpi_gpe_en_reg_0 = GPIO_EAST2_GPI_GPE_EN,
+		.gpi_nmi_sts_reg_0 = GPIO_EAST2_NMI_STS,
+		.gpi_nmi_en_reg_0 = GPIO_EAST2_NMI_EN,
+		.pad_cfg_base = GPIO_EAST2_PADCFG_OFFSET,
+		.pad_cfg_lock_offset = GPIO_EAST2_PADCFGLOCK,
+		.gpi_status_offset = GPIO_WEST2_GPI_STATUS_REGS + GPIO_WEST3_GPI_STATUS_REGS +
+				     GPIO_WEST01_GPI_STATUS_REGS + GPIO_WEST5_GPI_STATUS_REGS +
+				     GPIO_WESTB_GPI_STATUS_REGS +
+				     GPIO_WESTD_PECI_GPI_STATUS_REGS,
+		.port = PID_GPIOCOM0,
+		.groups = snr_community_east2_groups,
+		.num_groups = ARRAY_SIZE(snr_community_east2_groups),
+	},
+	{
+		.name = "GPIO_EAST3",
+		.acpi_path = "\\_SB.GPO12",
+		.num_gpi_regs = GPIO_EAST3_GPI_STATUS_REGS,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.first_pad = GPIO_EAST3_0,
+		.last_pad = GPIO_EAST3_9,
+		.pad_own_reg_0 = GPIO_EAST3_PAD_OWN,
+		.host_own_reg_0 = GPIO_EAST3_HOSTSW_OWN,
+		.gpi_int_sts_reg_0 = GPIO_EAST3_GPI_IS,
+		.gpi_int_en_reg_0 = GPIO_EAST3_GPI_IE,
+		.gpi_smi_sts_reg_0 = GPIO_EAST3_SMI_STS,
+		.gpi_smi_en_reg_0 = GPIO_EAST3_SMI_EN,
+		.gpi_gpe_sts_reg_0 = GPIO_EAST3_GPI_GPE_STS,
+		.gpi_gpe_en_reg_0 = GPIO_EAST3_GPI_GPE_EN,
+		.gpi_nmi_sts_reg_0 = GPIO_EAST3_NMI_STS,
+		.gpi_nmi_en_reg_0 = GPIO_EAST3_NMI_EN,
+		.pad_cfg_base = GPIO_EAST3_PADCFG_OFFSET,
+		.pad_cfg_lock_offset = GPIO_EAST3_PADCFGLOCK,
+		.gpi_status_offset = GPIO_WEST2_GPI_STATUS_REGS + GPIO_WEST3_GPI_STATUS_REGS +
+				     GPIO_WEST01_GPI_STATUS_REGS + GPIO_WEST5_GPI_STATUS_REGS +
+				     GPIO_WESTB_GPI_STATUS_REGS +
+				     GPIO_WESTD_PECI_GPI_STATUS_REGS +
+				     GPIO_EAST2_GPI_STATUS_REGS,
+		.port = PID_GPIOCOM0,
+		.groups = snr_community_east3_groups,
+		.num_groups = ARRAY_SIZE(snr_community_east3_groups),
+	},
+	{
+		.name = "GPIO_EAST0",
+		.acpi_path = "\\_SB.GPO13",
+		.num_gpi_regs = GPIO_EAST0_GPI_STATUS_REGS,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.first_pad = GPIO_EAST0_0,
+		.last_pad = GPIO_EAST0_22,
+		.pad_own_reg_0 = GPIO_EAST0_PAD_OWN,
+		.host_own_reg_0 = GPIO_EAST0_HOSTSW_OWN,
+		.gpi_int_sts_reg_0 = GPIO_EAST0_GPI_IS,
+		.gpi_int_en_reg_0 = GPIO_EAST0_GPI_IE,
+		.gpi_smi_sts_reg_0 = GPIO_EAST0_SMI_STS,
+		.gpi_smi_en_reg_0 = GPIO_EAST0_SMI_EN,
+		.gpi_gpe_sts_reg_0 = GPIO_EAST0_GPI_GPE_STS,
+		.gpi_gpe_en_reg_0 = GPIO_EAST0_GPI_GPE_EN,
+		.gpi_nmi_sts_reg_0 = GPIO_EAST0_NMI_STS,
+		.gpi_nmi_en_reg_0 = GPIO_EAST0_NMI_EN,
+		.pad_cfg_base = GPIO_EAST0_PADCFG_OFFSET,
+		.pad_cfg_lock_offset = GPIO_EAST0_PADCFGLOCK,
+		.gpi_status_offset = GPIO_WEST2_GPI_STATUS_REGS + GPIO_WEST3_GPI_STATUS_REGS +
+				     GPIO_WEST01_GPI_STATUS_REGS + GPIO_WEST5_GPI_STATUS_REGS +
+				     GPIO_WESTB_GPI_STATUS_REGS +
+				     GPIO_WESTD_PECI_GPI_STATUS_REGS +
+				     GPIO_EAST2_GPI_STATUS_REGS + GPIO_EAST3_GPI_STATUS_REGS,
+		.port = PID_GPIOCOM0,
+		.groups = snr_community_east0_groups,
+		.num_groups = ARRAY_SIZE(snr_community_east0_groups),
+	},
+	{
+		.name = "GPIO_EMMC",
+		.acpi_path = "\\_SB.GPO14",
+		.num_gpi_regs = GPIO_EMMC_GPI_STATUS_REGS,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.first_pad = GPIO_EMMC_0,
+		.last_pad = GPIO_EMMC_10,
+		.pad_own_reg_0 = GPIO_EMMC_PAD_OWN,
+		.host_own_reg_0 = GPIO_EMMC_HOSTSW_OWN,
+		.gpi_int_sts_reg_0 = GPIO_EMMC_GPI_IS,
+		.gpi_int_en_reg_0 = GPIO_EMMC_GPI_IE,
+		.gpi_smi_sts_reg_0 = GPIO_EMMC_SMI_STS,
+		.gpi_smi_en_reg_0 = GPIO_EMMC_SMI_EN,
+		.gpi_gpe_sts_reg_0 = GPIO_EMMC_GPI_GPE_STS,
+		.gpi_gpe_en_reg_0 = GPIO_EMMC_GPI_GPE_EN,
+		.gpi_nmi_sts_reg_0 = GPIO_EMMC_NMI_STS,
+		.gpi_nmi_en_reg_0 = GPIO_EMMC_NMI_EN,
+		.pad_cfg_base = GPIO_EMMC_PADCFG_OFFSET,
+		.pad_cfg_lock_offset = GPIO_EMMC_PADCFGLOCK,
+		.gpi_status_offset = GPIO_WEST2_GPI_STATUS_REGS + GPIO_WEST3_GPI_STATUS_REGS +
+				     GPIO_WEST01_GPI_STATUS_REGS + GPIO_WEST5_GPI_STATUS_REGS +
+				     GPIO_WESTB_GPI_STATUS_REGS +
+				     GPIO_WESTD_PECI_GPI_STATUS_REGS +
+				     GPIO_EAST2_GPI_STATUS_REGS + GPIO_EAST3_GPI_STATUS_REGS +
+				     GPIO_EAST0_GPI_STATUS_REGS,
+		.port = PID_GPIOCOM0,
+		.groups = snr_community_emmc_groups,
+		.num_groups = ARRAY_SIZE(snr_community_emmc_groups),
+	}
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+	*num_communities = ARRAY_SIZE(snr_gpio_communities);
+	return snr_gpio_communities;
+}
diff --git a/src/soc/intel/snowridge/common/hob_display.c b/src/soc/intel/snowridge/common/hob_display.c
new file mode 100644
index 0000000000..eaed9c674b
--- /dev/null
+++ b/src/soc/intel/snowridge/common/hob_display.c
@@ -0,0 +1,312 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <fsp/debug.h>
+#include <fsp/soc_binding.h>
+#include <fsp/util.h>
+#include <lib.h>
+#include <uuid.h>
+
+#include "fsp_hob.h"
+
+struct guid_name_map {
+	const guid_t *guid;
+	const char *name;
+};
+
+static const struct guid_name_map guid_names[] = {
+	{&fsp_hob_fia_override_status_guid, "FSP_HOB_FIA_OVERRIDE_STATUS_GUID"},
+	{&fsp_hob_iio_uds_data_guid,        "FSP_HOB_IIO_UDS_DATA_GUID"       },
+	{&fsp_hob_kti_cache_guid,           "FSP_HOB_KTI_HOST_NVRAM_DATA_GUID"},
+	{&fsp_hob_smbios_memory_info_guid,  "FSP_HOB_SMBIOS_MEMORY_INFO_GUID" },
+};
+
+const char *soc_get_guid_name(const uint8_t *guid)
+{
+	size_t index;
+
+	/* Compare the GUID values in this module */
+	for (index = 0; index < ARRAY_SIZE(guid_names); index++)
+		if (fsp_guid_compare(guid, guid_names[index].guid->b))
+			return guid_names[index].name;
+
+	return NULL;
+}
+
+static void soc_display_fsp_iio_uds_data_hob(const BL_IIO_UDS *hob)
+{
+	if (!hob) {
+		return;
+	}
+
+	printk(BIOS_DEBUG, "IIO UDS\n");
+	printk(BIOS_DEBUG, "\t Platform Data\n");
+	printk(BIOS_DEBUG, "\t\t PlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase);
+	printk(BIOS_DEBUG, "\t\t PlatGlobalIoLimit: 0x%x\n",
+	       hob->PlatformData.PlatGlobalIoLimit);
+	printk(BIOS_DEBUG, "\t\t PlatGlobalMmio32Base: 0x%x\n",
+	       hob->PlatformData.PlatGlobalMmio32Base);
+	printk(BIOS_DEBUG, "\t\t PlatGlobalMmio32Limit: 0x%x\n",
+	       hob->PlatformData.PlatGlobalMmio32Limit);
+	printk(BIOS_DEBUG, "\t\t PlatGlobalMmio64Base: 0x%llx\n",
+	       hob->PlatformData.PlatGlobalMmio64Base);
+	printk(BIOS_DEBUG, "\t\t PlatGlobalMmio64Limit: 0x%llx\n",
+	       hob->PlatformData.PlatGlobalMmio64Limit);
+	for (int socket = 0; socket < BL_MAX_SOCKET; socket++) {
+		const BL_QPI_CPU_DATA *cpu_qpi_info = &hob->PlatformData.CpuQpiInfo[socket];
+		printk(BIOS_DEBUG, "\t\t CpuQpiInfo[%d]\n", socket);
+		printk(BIOS_DEBUG, "\t\t\t Valid: 0x%x\n", cpu_qpi_info->Valid);
+		for (int bar = 0; bar < BL_TYPE_MAX_MMIO_BAR; bar++) {
+			printk(BIOS_DEBUG, "\t\t\t MmioBar[%d]: 0x%x\n", bar,
+			       cpu_qpi_info->MmioBar[bar]);
+		}
+		printk(BIOS_DEBUG, "\t\t\t PcieSegment: 0x%x\n", cpu_qpi_info->PcieSegment);
+		printk(BIOS_DEBUG, "\t\t\t SegMmcfgBase: 0x%llx\n",
+		       cpu_qpi_info->SegMmcfgBase.Data);
+		printk(BIOS_DEBUG, "\t\t\t stackPresentBitmap: 0x%x\n",
+		       cpu_qpi_info->stackPresentBitmap);
+		printk(BIOS_DEBUG, "\t\t\t M2PciePresentBitmap: 0x%x\n",
+		       cpu_qpi_info->M2PciePresentBitmap);
+		printk(BIOS_DEBUG, "\t\t\t TotM3Kti: 0x%x\n", cpu_qpi_info->TotM3Kti);
+		printk(BIOS_DEBUG, "\t\t\t TotCha: 0x%x\n", cpu_qpi_info->TotCha);
+		for (int cha = 0; cha < BL_MAX_CHA_MAP; cha++) {
+			printk(BIOS_DEBUG, "\t\t\t ChaList[%d]: 0x%x\n", cha,
+			       cpu_qpi_info->ChaList[cha]);
+		}
+		printk(BIOS_DEBUG, "\t\t\t SocId: 0x%x\n", cpu_qpi_info->SocId);
+		for (int peer = 0; peer < BL_MAX_FW_KTI_PORTS; peer++) {
+			const BL_QPI_PEER_DATA *peer_info = &cpu_qpi_info->PeerInfo[peer];
+			printk(BIOS_DEBUG, "\t\t\t PeerInfo[%d]\n", peer);
+			printk(BIOS_DEBUG, "\t\t\t\t Valid: 0x%x\n", peer_info->Valid);
+			printk(BIOS_DEBUG, "\t\t\t\t PeerSocId: 0x%x\n", peer_info->PeerSocId);
+			printk(BIOS_DEBUG, "\t\t\t\t PeerSocType: 0x%x\n",
+			       peer_info->PeerSocType);
+			printk(BIOS_DEBUG, "\t\t\t\t PeerPort: 0x%x\n", peer_info->PeerPort);
+		}
+	}
+	for (int socket = 0; socket < BL_MAX_SOCKET; socket++) {
+		const BL_QPI_IIO_DATA *iio_qpi_info = &hob->PlatformData.IioQpiInfo[socket];
+		printk(BIOS_DEBUG, "\t\t IioQpiInfo[%d]\n", socket);
+		printk(BIOS_DEBUG, "\t\t\t SocId: 0x%x\n", iio_qpi_info->SocId);
+		for (int peer = 0; peer < BL_MAX_SOCKET; peer++) {
+			const BL_QPI_PEER_DATA *peer_info = &iio_qpi_info->PeerInfo[peer];
+			printk(BIOS_DEBUG, "\t\t\t PeerInfo[%d]\n", peer);
+			printk(BIOS_DEBUG, "\t\t\t\t Valid: 0x%x\n", peer_info->Valid);
+			printk(BIOS_DEBUG, "\t\t\t\t PeerSocId: 0x%x\n", peer_info->PeerSocId);
+			printk(BIOS_DEBUG, "\t\t\t\t PeerSocType: 0x%x\n",
+			       peer_info->PeerSocType);
+			printk(BIOS_DEBUG, "\t\t\t\t PeerPort: 0x%x\n", peer_info->PeerPort);
+		}
+	}
+	printk(BIOS_DEBUG, "\t\t MemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize);
+	printk(BIOS_DEBUG, "\t\t MemIedSize: 0x%x\n", hob->PlatformData.MemIedSize);
+	printk(BIOS_DEBUG, "\t\t PciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase);
+	printk(BIOS_DEBUG, "\t\t PciExpressSize: 0x%x\n", hob->PlatformData.PciExpressSize);
+	printk(BIOS_DEBUG, "\t\t MemTolm: 0x%x\n", hob->PlatformData.MemTolm);
+	for (uint8_t socket = 0; socket < hob->PlatformData.numofIIO; socket++) {
+		const BL_IIO_RESOURCE_INSTANCE *iio_res =
+			&hob->PlatformData.IIO_resource[socket];
+		printk(BIOS_DEBUG, "\t\t IIO_resource[%d]\n", socket);
+		printk(BIOS_DEBUG, "\t\t\t Valid: 0x%x\n", iio_res->Valid);
+		printk(BIOS_DEBUG, "\t\t\t SocketID: 0x%x\n", iio_res->SocketID);
+		printk(BIOS_DEBUG, "\t\t\t BusBase: 0x%x\n", iio_res->BusBase);
+		printk(BIOS_DEBUG, "\t\t\t BusLimit: 0x%x\n", iio_res->BusLimit);
+		printk(BIOS_DEBUG, "\t\t\t PciResourceIoBase: 0x%x\n",
+		       iio_res->PciResourceIoBase);
+		printk(BIOS_DEBUG, "\t\t\t PciResourceIoLimit: 0x%x\n",
+		       iio_res->PciResourceIoLimit);
+		printk(BIOS_DEBUG, "\t\t\t IoApicBase: 0x%x\n", iio_res->IoApicBase);
+		printk(BIOS_DEBUG, "\t\t\t IoApicLimit: 0x%x\n", iio_res->IoApicLimit);
+		printk(BIOS_DEBUG, "\t\t\t Mmio32Base: 0x%x\n", iio_res->Mmio32Base);
+		printk(BIOS_DEBUG, "\t\t\t Mmio32Limit: 0x%x\n", iio_res->Mmio32Limit);
+		printk(BIOS_DEBUG, "\t\t\t Mmio64Base: 0x%llx\n", iio_res->Mmio64Base);
+		printk(BIOS_DEBUG, "\t\t\t Mmio64Limit: 0x%llx\n", iio_res->Mmio64Limit);
+		for (int stack = 0; stack < BL_MAX_LOGIC_IIO_STACK; stack++) {
+			const BL_STACK_RES *stack_res = &iio_res->StackRes[stack];
+			printk(BIOS_DEBUG, "\t\t\t StackRes[%d]\n", stack);
+			printk(BIOS_DEBUG, "\t\t\t\t Personality: 0x%x\n",
+			       stack_res->Personality);
+			printk(BIOS_DEBUG, "\t\t\t\t BusBase: 0x%x\n", stack_res->BusBase);
+			printk(BIOS_DEBUG, "\t\t\t\t BusLimit: 0x%x\n", stack_res->BusLimit);
+			printk(BIOS_DEBUG, "\t\t\t\t PciResourceIoBase: 0x%x\n",
+			       stack_res->PciResourceIoBase);
+			printk(BIOS_DEBUG, "\t\t\t\t PciResourceIoLimit: 0x%x\n",
+			       stack_res->PciResourceIoLimit);
+			printk(BIOS_DEBUG, "\t\t\t\t IoApicBase: 0x%x\n",
+			       stack_res->IoApicBase);
+			printk(BIOS_DEBUG, "\t\t\t\t IoApicLimit: 0x%x\n",
+			       stack_res->IoApicLimit);
+			printk(BIOS_DEBUG, "\t\t\t\t Mmio32Base: 0x%x\n",
+			       stack_res->Mmio32Base);
+			printk(BIOS_DEBUG, "\t\t\t\t Mmio32Limit: 0x%x\n",
+			       stack_res->Mmio32Limit);
+			printk(BIOS_DEBUG, "\t\t\t\t Mmio64Base: 0x%llx\n",
+			       stack_res->Mmio64Base);
+			printk(BIOS_DEBUG, "\t\t\t\t Mmio64Limit: 0x%llx\n",
+			       stack_res->Mmio64Limit);
+			printk(BIOS_DEBUG, "\t\t\t\t PciResourceMem32Base: 0x%x\n",
+			       stack_res->PciResourceMem32Base);
+			printk(BIOS_DEBUG, "\t\t\t\t PciResourceMem32Limit: 0x%x\n",
+			       stack_res->PciResourceMem32Limit);
+			printk(BIOS_DEBUG, "\t\t\t\t PciResourceMem64Base: 0x%llx\n",
+			       stack_res->PciResourceMem64Base);
+			printk(BIOS_DEBUG, "\t\t\t\t PciResourceMem64Limit: 0x%llx\n",
+			       stack_res->PciResourceMem64Limit);
+			printk(BIOS_DEBUG, "\t\t\t\t VtdBarAddress: 0x%x\n",
+			       stack_res->VtdBarAddress);
+			printk(BIOS_DEBUG, "\t\t\t\t Mmio32MinSize: 0x%x\n",
+			       stack_res->Mmio32MinSize);
+		}
+		printk(BIOS_DEBUG, "\t\t\t RcBaseAddress: 0x%x\n", iio_res->RcBaseAddress);
+		printk(BIOS_DEBUG, "\t\t\t PcieInfo\n");
+		for (int port = 0; port < BL_NUMBER_PORTS_PER_SOCKET; port++) {
+			const BL_IIO_PORT_INFO *port_info = &iio_res->PcieInfo.PortInfo[port];
+			printk(BIOS_DEBUG, "\t\t\t\t PortInfo[%d]\n", port);
+			printk(BIOS_DEBUG, "\t\t\t\t\t Device: 0x%x, Function: 0x%x\n",
+			       port_info->Device, port_info->Function);
+		}
+		printk(BIOS_DEBUG, "\t\t\t DmaDeviceCount: 0x%x\n", iio_res->DmaDeviceCount);
+	}
+	printk(BIOS_DEBUG, "\t\t numofIIO: 0x%x\n", hob->PlatformData.numofIIO);
+	printk(BIOS_DEBUG, "\t\t MaxBusNumber: 0x%x\n", hob->PlatformData.MaxBusNumber);
+	for (int socket = 0; socket < BL_MAX_SOCKET; socket++) {
+		printk(BIOS_DEBUG, "\t\t packageBspApicID[%d]: 0x%x\n", socket,
+		       hob->PlatformData.packageBspApicID[socket]);
+	}
+	printk(BIOS_DEBUG, "\t\t EVMode: 0x%x\n", hob->PlatformData.EVMode);
+	printk(BIOS_DEBUG, "\t\t Pci64BitResourceAllocation: %d\n",
+	       hob->PlatformData.Pci64BitResourceAllocation);
+	for (int socket = 0; socket < BL_MAX_SOCKET; socket++) {
+		printk(BIOS_DEBUG, "\t\t SkuPersonality[%d]: 0x%x\n", socket,
+		       hob->PlatformData.SkuPersonality[socket]);
+	}
+	for (int iio = 0; iio < BL_MaxIIO; iio++) {
+		for (int iio_stack = 0; iio_stack < BL_MAX_IIO_STACK; iio_stack++) {
+			printk(BIOS_DEBUG, "\t\t VMDStackEnable[%d][%d]: 0x%x\n", iio,
+			       iio_stack, hob->PlatformData.VMDStackEnable[iio][iio_stack]);
+		}
+	}
+	printk(BIOS_DEBUG, "\t\t IoGranularity: 0x%x\n", hob->PlatformData.IoGranularity);
+	printk(BIOS_DEBUG, "\t\t MmiolGranularity: 0x%x\n", hob->PlatformData.MmiolGranularity);
+	printk(BIOS_DEBUG, "\t\t MmiohGranularity: 0x%llx\n",
+	       hob->PlatformData.MmiohGranularity.Data);
+	printk(BIOS_DEBUG, "\t\t RemoteRequestThreshold: 0x%x\n",
+	       hob->PlatformData.RemoteRequestThreshold);
+	printk(BIOS_DEBUG, "\t\t UboxMmioSize: 0x%x\n", hob->PlatformData.UboxMmioSize);
+	printk(BIOS_DEBUG, "\t\t MaxAddressBits: 0x%x\n", hob->PlatformData.MaxAddressBits);
+
+	printk(BIOS_DEBUG, "\t System Status\n");
+	printk(BIOS_DEBUG, "\t\t CurrentUpiiLinkSpeed: 0x%x\n",
+	       hob->SystemStatus.CurrentUpiiLinkSpeed);
+	printk(BIOS_DEBUG, "\t\t CurrentUpiLinkFrequency: 0x%x\n",
+	       hob->SystemStatus.CurrentUpiLinkFrequency);
+	printk(BIOS_DEBUG, "\t\t OutKtiCpuSktHotPlugEn: 0x%x\n",
+	       hob->SystemStatus.OutKtiCpuSktHotPlugEn);
+	for (int socket = 0; socket < BL_MAX_SOCKET; socket++)
+		printk(BIOS_DEBUG, "\t\t OutKtiPerLinkL1En: 0x%x\n",
+		       hob->SystemStatus.OutKtiPerLinkL1En[socket]);
+	printk(BIOS_DEBUG, "\t\t IsocEnable: 0x%x\n", hob->SystemStatus.IsocEnable);
+	printk(BIOS_DEBUG, "\t\t meRequestedSize: 0x%x\n", hob->SystemStatus.meRequestedSize);
+	printk(BIOS_DEBUG, "\t\t ieRequestedSize: 0x%x\n", hob->SystemStatus.ieRequestedSize);
+	printk(BIOS_DEBUG, "\t\t DmiVc1: 0x%x\n", hob->SystemStatus.DmiVc1);
+	printk(BIOS_DEBUG, "\t\t DmiVcm: 0x%x\n", hob->SystemStatus.DmiVcm);
+	printk(BIOS_DEBUG, "\t\t CpuPCPSInfo: 0x%x\n", hob->SystemStatus.CpuPCPSInfo);
+	printk(BIOS_DEBUG, "\t\t cpuSubType: 0x%x\n", hob->SystemStatus.cpuSubType);
+	printk(BIOS_DEBUG, "\t\t SystemRasType: 0x%x\n", hob->SystemStatus.SystemRasType);
+	printk(BIOS_DEBUG, "\t\t numCpus: 0x%x\n", hob->SystemStatus.numCpus);
+	printk(BIOS_DEBUG, "\t\t tolmLimit: 0x%x\n", hob->SystemStatus.tolmLimit);
+	printk(BIOS_DEBUG, "\t\t tohmLimit: 0x%x\n", hob->SystemStatus.tohmLimit);
+	printk(BIOS_DEBUG, "\t\t RcVersion\n");
+	printk(BIOS_DEBUG, "\t\t\t Major: 0x%x\n", hob->SystemStatus.RcVersion.Major);
+	printk(BIOS_DEBUG, "\t\t\t Minor: 0x%x\n", hob->SystemStatus.RcVersion.Minor);
+	printk(BIOS_DEBUG, "\t\t\t Revision: 0x%x\n", hob->SystemStatus.RcVersion.Revision);
+	printk(BIOS_DEBUG, "\t\t\t BuildNumber: 0x%x\n",
+	       hob->SystemStatus.RcVersion.BuildNumber);
+	printk(BIOS_DEBUG, "\t\t MsrTraceEnable: 0x%x\n", hob->SystemStatus.MsrTraceEnable);
+	printk(BIOS_DEBUG, "\t\t DdrXoverMode: 0x%x\n", hob->SystemStatus.DdrXoverMode);
+	printk(BIOS_DEBUG, "\t\t bootMode: 0x%x\n", hob->SystemStatus.bootMode);
+	printk(BIOS_DEBUG, "\t\t OutClusterOnDieEn: 0x%x\n",
+	       hob->SystemStatus.OutClusterOnDieEn);
+	printk(BIOS_DEBUG, "\t\t OutSncEn: 0x%x\n", hob->SystemStatus.OutSncEn);
+	printk(BIOS_DEBUG, "\t\t OutNumOfCluster: 0x%x\n", hob->SystemStatus.OutNumOfCluster);
+	for (int socket = 0; socket < BL_MAX_SOCKET; socket++) {
+		for (int imc = 0; imc < BL_MAX_IMC; imc++) {
+			printk(BIOS_DEBUG, "\t\t imcEnabled[%d][%d]: 0x%x\n", socket, imc,
+			       hob->SystemStatus.imcEnabled[socket][imc]);
+		}
+	}
+	printk(BIOS_DEBUG, "\t\t LlcSizeReg: 0x%x\n", hob->SystemStatus.LlcSizeReg);
+	for (int socket = 0; socket < BL_MAX_SOCKET; socket++) {
+		for (int ch = 0; ch < BL_MAX_CH; ch++) {
+			printk(BIOS_DEBUG, "\t\t chEnabled[%d][%d]: 0x%x\n", socket, ch,
+			       hob->SystemStatus.chEnabled[socket][ch]);
+		}
+	}
+	for (int node = 0; node < BL_MC_MAX_NODE; node++) {
+		printk(BIOS_DEBUG, "\t\t memNode[%d]: 0x%x\n", node,
+		       hob->SystemStatus.memNode[node]);
+	}
+	printk(BIOS_DEBUG, "\t\t IoDcMode: 0x%x\n", hob->SystemStatus.IoDcMode);
+	printk(BIOS_DEBUG, "\t\t DfxRstCplBitsEn: 0x%x\n", hob->SystemStatus.DfxRstCplBitsEn);
+}
+
+static void soc_display_fsp_fia_override_status(const BL_FIA_OVERRIDE_STATUS_HOB *hob)
+{
+	if (!hob)
+		return;
+	printk(BIOS_DEBUG, "FIA Override Status\n");
+	printk(BIOS_DEBUG, "\t FiaMuxConfigGetStatus: 0x%08x\n", hob->FiaMuxConfigGetStatus);
+	printk(BIOS_DEBUG, "\t FiaMuxConfigSetStatus: 0x%08x\n", hob->FiaMuxConfigSetStatus);
+	printk(BIOS_DEBUG, "\t FiaMuxConfigSetRequired: 0x%08x\n",
+	       hob->FiaMuxConfigSetRequired);
+}
+
+static void soc_display_fsp_smbios_memory_info(const FSP_SMBIOS_MEMORY_INFO *hob)
+{
+	if (!hob)
+		return;
+
+	printk(BIOS_DEBUG, "SMBIOS Memory Info\n");
+	printk(BIOS_DEBUG, "\t Revision: 0x%x\n", hob->Revision);
+	printk(BIOS_DEBUG, "\t DataWidth: 0x%x\n", hob->DataWidth);
+	printk(BIOS_DEBUG, "\t MemoryType: 0x%x\n", hob->MemoryType);
+	printk(BIOS_DEBUG, "\t MemoryFrequencyInMHz: 0x%x\n", hob->MemoryFrequencyInMHz);
+	printk(BIOS_DEBUG, "\t ErrorCorrectionType: 0x%x\n", hob->ErrorCorrectionType);
+	printk(BIOS_DEBUG, "\t ChannelCount: 0x%x\n", hob->ChannelCount);
+	for (uint8_t channel = 0; channel < hob->ChannelCount; channel++) {
+		const CHANNEL_INFO *channel_info = &hob->ChannelInfo[channel];
+		printk(BIOS_DEBUG, "\t ChannelInfo[%d]\n", channel);
+		printk(BIOS_DEBUG, "\t\t ChannelId: 0x%x\n", channel_info->ChannelId);
+		printk(BIOS_DEBUG, "\t\t DimmCount: 0x%x\n", channel_info->DimmCount);
+		for (uint8_t dimm = 0; dimm < channel_info->DimmCount; dimm++) {
+			const DIMM_INFO *dimm_info = &channel_info->DimmInfo[dimm];
+			printk(BIOS_DEBUG, "\t\t\t DimmInfo[%d]\n", dimm);
+			printk(BIOS_DEBUG, "\t\t\t\t DimmId: 0x%x\n", dimm_info->DimmId);
+			printk(BIOS_DEBUG, "\t\t\t\t SizeInMb: 0x%x\n", dimm_info->SizeInMb);
+			printk(BIOS_DEBUG, "\t\t\t\t MfgId: 0x%x\n", dimm_info->MfgId);
+			printk(BIOS_DEBUG, "\t\t\t\t ModulePartNum: %s\n",
+			       dimm_info->ModulePartNum);
+		}
+	}
+}
+
+void soc_display_hob(const struct hob_header *hob)
+{
+	uint8_t *guid;
+
+	if (hob->type != HOB_TYPE_GUID_EXTENSION)
+		return;
+
+	guid = (uint8_t *)fsp_hob_header_to_resource(hob);
+	if (fsp_guid_compare(guid, fsp_hob_iio_uds_data_guid.b))
+		soc_display_fsp_iio_uds_data_hob(
+			(const BL_IIO_UDS *)(guid + sizeof(fsp_hob_iio_uds_data_guid)));
+	else if (fsp_guid_compare(guid, fsp_hob_fia_override_status_guid.b))
+		soc_display_fsp_fia_override_status(
+			(const BL_FIA_OVERRIDE_STATUS_HOB
+				 *)(guid + sizeof(fsp_hob_fia_override_status_guid)));
+	else if (fsp_guid_compare(guid, fsp_hob_smbios_memory_info_guid.b))
+		soc_display_fsp_smbios_memory_info(
+			(const FSP_SMBIOS_MEMORY_INFO
+				 *)(guid + sizeof(fsp_hob_smbios_memory_info_guid)));
+}
diff --git a/src/soc/intel/snowridge/common/kti_cache.c b/src/soc/intel/snowridge/common/kti_cache.c
new file mode 100644
index 0000000000..f3d72b638d
--- /dev/null
+++ b/src/soc/intel/snowridge/common/kti_cache.c
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot_device.h>
+#include <bootstate.h>
+#include <commonlib/bsd/ipchksum.h>
+#include <stdlib.h>
+#include <commonlib/region.h>
+#include <console/console.h>
+#include <fmap.h>
+#include <lib.h>
+#include <spi-generic.h>
+#include <spi_flash.h>
+#include <string.h>
+
+#include "fsp_hob.h"
+#include "kti_cache.h"
+
+struct kti_metadata {
+	uint16_t data_size;
+	uint16_t data_checksum;
+} __packed;
+
+void *kti_cache_load(size_t *size)
+{
+	struct region region;
+	struct region_device read_rdev;
+	struct kti_metadata md;
+	void *data;
+	uint16_t checksum;
+
+	if (fmap_locate_area(CONFIG_KTI_CACHE_FMAP_NAME, &region) != 0) {
+		printk(BIOS_ERR, "Region %s doesn't exist!\n", CONFIG_KTI_CACHE_FMAP_NAME);
+		return NULL;
+	}
+
+	if (boot_device_ro_subregion(&region, &read_rdev) < 0)
+		return NULL;
+
+	if (rdev_readat(&read_rdev, &md, 0, sizeof(struct kti_metadata)) < 0) {
+		printk(BIOS_ERR, "Couldn't read KTI metadata\n");
+		return NULL;
+	}
+
+	if (md.data_size == 0xFFFF) {
+		printk(BIOS_INFO, "KTI cache not found!\n");
+		return NULL;
+	}
+
+	data = rdev_mmap(&read_rdev, sizeof(struct kti_metadata), md.data_size);
+	if (data == NULL) {
+		printk(BIOS_ERR, "Map KTI cache failed.\n");
+		return NULL;
+	}
+
+	checksum = ipchksum(data, md.data_size);
+	rdev_munmap(&read_rdev, data);
+	if (checksum != md.data_checksum) {
+		printk(BIOS_ERR, "KTI cache checksum mismatch: %x vs %x\n", md.data_checksum,
+		       checksum);
+		return NULL;
+	}
+
+	if (size)
+		*size = md.data_size;
+
+	return data;
+}
+
+static void kti_cache_protect(void)
+{
+	struct region region;
+
+	if (fmap_locate_area(CONFIG_KTI_CACHE_FMAP_NAME, &region) < 0) {
+		return;
+	}
+
+	if (spi_flash_ctrlr_protect_region(boot_device_spi_flash(), &region, WRITE_PROTECT) <
+	    0) {
+		printk(BIOS_ERR, "Set Flash Protected Range for %s failed.\n",
+		       CONFIG_KTI_CACHE_FMAP_NAME);
+		return;
+	}
+
+	printk(BIOS_INFO, "Enable Flash Protected Range on %s.\n", CONFIG_KTI_CACHE_FMAP_NAME);
+}
+
+static void kti_cache_save(void *unused)
+{
+	size_t kti_data_size;
+	const void *kti_data;
+	struct kti_metadata *md;
+	struct region region;
+	struct region_device write_rdev;
+
+	printk(BIOS_INFO, "Save KTI starts...\n");
+
+	kti_data = fsp_hob_get_kti_cache(&kti_data_size);
+	if (!kti_data) {
+		printk(BIOS_WARNING, "Couldn't find KTI cache hob!\n");
+		return;
+	}
+
+	hexdump(kti_data, kti_data_size);
+
+	md = malloc(sizeof(struct kti_metadata) + kti_data_size);
+	if (md == NULL) {
+		printk(BIOS_ERR, "Allocate KTI metadata failed!\n");
+		return;
+	}
+
+	memset(md, 0, sizeof(struct kti_metadata));
+	md->data_size = kti_data_size;
+	md->data_checksum = ipchksum(kti_data, kti_data_size);
+	memcpy(md + 1, kti_data, kti_data_size);
+
+	if (fmap_locate_area(CONFIG_KTI_CACHE_FMAP_NAME, &region) != 0)
+		goto ret;
+
+	if (boot_device_rw_subregion(&region, &write_rdev) < 0)
+		goto ret;
+
+	if (rdev_eraseat(&write_rdev, 0, region_device_sz(&write_rdev)) < 0) {
+		printk(BIOS_ERR, "Erase stale KTI cache failed.\n");
+		goto ret;
+	}
+
+	if (rdev_writeat(&write_rdev, md, 0, sizeof(struct kti_metadata) + kti_data_size) < 0) {
+		printk(BIOS_ERR, "Write KTI cache failed.\n");
+		goto ret;
+	}
+
+	kti_cache_protect();
+
+	printk(BIOS_INFO, "Save KTI ends.\n");
+
+ret:
+	free(md);
+}
+
+/**
+ * Ensures kti data is stored into SPI after PCI enumeration is done during
+ * BS_DEV_ENUMERATE-BS_ON_EXIT and lock down SPI protected ranges during
+ * BS_DEV_RESOURCES-BS_ON_EXIT.
+ */
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, kti_cache_save, NULL);
diff --git a/src/soc/intel/snowridge/common/kti_cache.h b/src/soc/intel/snowridge/common/kti_cache.h
new file mode 100644
index 0000000000..0c8d923e33
--- /dev/null
+++ b/src/soc/intel/snowridge/common/kti_cache.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_SNOWRIDGE_KTI_CACHE_H_
+#define _SOC_SNOWRIDGE_KTI_CACHE_H_
+
+#include <stddef.h>
+
+void *kti_cache_load(size_t *size);
+
+#endif // _SOC_SNOWRIDGE_KTI_CACHE_H_
diff --git a/src/soc/intel/snowridge/common/pmclib.c b/src/soc/intel/snowridge/common/pmclib.c
new file mode 100644
index 0000000000..ae995ca67c
--- /dev/null
+++ b/src/soc/intel/snowridge/common/pmclib.c
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <intelblocks/pmclib.h>
+#include <soc/iomap.h>
+#include <soc/pm.h>
+#include <soc/pmc.h>
+
+const char *const *soc_smi_sts_array(size_t *a)
+{
+	static const char *const smi_sts_bits[] = {
+		[BIOS_STS_BIT] = "BIOS",
+		[LEGACY_USB_STS_BIT] = "LEGACY_USB",
+		[SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
+		[APM_STS_BIT] = "APM",
+		[SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
+		[PM1_STS_BIT] = "PM1",
+		[GPE0_STS_BIT] = "GPE0",
+		[GPIO_STS_BIT] = "GPI",
+		[MCSMI_STS_BIT] = "MCSMI",
+		[DEVMON_STS_BIT] = "DEVMON",
+		[TCO_STS_BIT] = "TCO",
+		[PERIODIC_STS_BIT] = "PERIODIC",
+		[SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
+		[SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
+		[PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
+		[MONITOR_STS_BIT] = "MONITOR",
+		[SPI_SMI_STS_BIT] = "SPI",
+		[GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
+		[ESPI_SMI_STS_BIT] = "ESPI_SMI",
+	};
+
+	*a = ARRAY_SIZE(smi_sts_bits);
+	return smi_sts_bits;
+}
+
+const char *const *soc_tco_sts_array(size_t *a)
+{
+	static const char *const tco_sts_bits[] = {
+		[0] = "NMI2SMI",
+		[1] = "SW_TCO",
+		[2] = "TCO_INT",
+		[3] = "TIMEOUT",
+		[7] = "NEWCENTURY",
+		[8] = "BIOSWR",
+		[9] = "DMISCI",
+		[10] = "DMISMI",
+		[12] = "DMISERR",
+		[13] = "SLVSEL",
+		[16] = "INTRD_DET",
+		[17] = "SECOND_TO",
+		[18] = "BOOT",
+		[20] = "SMLINK_SLV"
+	};
+
+	*a = ARRAY_SIZE(tco_sts_bits);
+	return tco_sts_bits;
+}
+
+const char *const *soc_std_gpe_sts_array(size_t *a)
+{
+	static const char *const gpe_sts_bits[] = {
+		[1] = "HOTPLUG",
+		[2] = "SWGPE",
+		[6] = "TCO_SCI",
+		[7] = "SMB_WAK",
+		[9] = "PCI_EXP",
+		[10] = "BATLOW",
+		[11] = "PME",
+		[12] = "ME",
+		[13] = "PME_B0",
+		[14] = "eSPI",
+		[15] = "GPIO Tier-2",
+		[16] = "LAN_WAKE",
+		[18] = "WADT"
+	};
+
+	*a = ARRAY_SIZE(gpe_sts_bits);
+	return gpe_sts_bits;
+}
+
+void pmc_soc_set_afterg3_en(bool on)
+{
+	uintptr_t pmc_bar = soc_read_pmc_base();
+	uint8_t reg8 = read32p(pmc_bar + GEN_PMCON_A);
+
+	if (on)
+		reg8 &= ~SLEEP_AFTER_POWER_FAIL;
+	else
+		reg8 |= SLEEP_AFTER_POWER_FAIL;
+
+	write32p(pmc_bar + GEN_PMCON_A, reg8);
+}
+
+uintptr_t soc_read_pmc_base(void)
+{
+	return PCH_PWRM_BASE_ADDRESS;
+}
+
+uint32_t *soc_pmc_etr_addr(void)
+{
+	return (uint32_t *)(soc_read_pmc_base() + ETR);
+}
diff --git a/src/soc/intel/snowridge/common/reset.c b/src/soc/intel/snowridge/common/reset.c
new file mode 100644
index 0000000000..dc2c5642e0
--- /dev/null
+++ b/src/soc/intel/snowridge/common/reset.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cf9_reset.h>
+#include <console/console.h>
+#include <soc/intel/common/reset.h>
+
+void do_global_reset(void)
+{
+	do_full_reset();
+}
diff --git a/src/soc/intel/snowridge/common/spi.c b/src/soc/intel/snowridge/common/spi.c
new file mode 100644
index 0000000000..7fbb9115b8
--- /dev/null
+++ b/src/soc/intel/snowridge/common/spi.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/spi.h>
+
+int spi_soc_devfn_to_bus(unsigned int devfn)
+{
+	return -1;
+}
diff --git a/src/soc/intel/snowridge/common/systemagent_early.c b/src/soc/intel/snowridge/common/systemagent_early.c
new file mode 100644
index 0000000000..56bddad500
--- /dev/null
+++ b/src/soc/intel/snowridge/common/systemagent_early.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/systemagent_server.h>
+#include <soc/systemagent.h>
+
+uint32_t sa_server_soc_reg_to_pci_offset(enum sa_server_reg reg)
+{
+	switch (reg) {
+	case MMCFG_BASE_REG:
+		return PCIE_MMCFG_BASE;
+	case MMCFG_LIMIT_REG:
+		return PCIE_MMCFG_LIMIT;
+	case TSEG_BASE_REG:
+		return TSEG;
+	case TSEG_LIMIT_REG:
+		return TSEG_LIMIT;
+	case TOCM_REG:
+		return TOCM;
+	case TOUUD_REG:
+		return TOUUD;
+	case TOLUD_REG:
+		return TOLUD;
+	case MMIO_L_REG:
+		return MMIOL;
+	case VT_BAR_REG:
+		return VTBAR;
+	case DPR_REG:
+		return DPR;
+	default:
+		return 0;
+	}
+}
diff --git a/src/soc/intel/snowridge/common/uart8250mem.c b/src/soc/intel/snowridge/common/uart8250mem.c
new file mode 100644
index 0000000000..51d0604ac8
--- /dev/null
+++ b/src/soc/intel/snowridge/common/uart8250mem.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/uart.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+
+#include "uart8250mem.h"
+
+uintptr_t uart_platform_base(unsigned int idx)
+{
+	uint32_t reg32 = pci_read_config32(PCH_DEV_UART(idx), UART_MEMBA);
+
+	reg32 &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+
+	return reg32;
+}
+
+unsigned int uart_platform_refclk(void)
+{
+	unsigned int ret = 115200 * 16;
+
+	/**
+	 * Base uart clock is HIGH_SPEED_CLK_MULT (24) * 1.8432Mhz if using baudrates > 115200.
+	 */
+	if (CONFIG_TTYS0_BAUD > 115200)
+		ret *= HIGH_SPEED_CLK_MULT;
+
+	return ret;
+}
diff --git a/src/soc/intel/snowridge/common/uart8250mem.h b/src/soc/intel/snowridge/common/uart8250mem.h
new file mode 100644
index 0000000000..2c5b6fb516
--- /dev/null
+++ b/src/soc/intel/snowridge/common/uart8250mem.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_SNOWRIDGE_UART_H_
+#define _SOC_SNOWRIDGE_UART_H_
+
+#define UART_IOBA   0x10
+#define UART_MEMBA  0x14
+
+#if CONFIG_CONSOLE_UART_BASE_ADDRESS != 0
+#define SIZE_OF_HSUART_RES 256
+#endif
+
+#define SNOWRIDGE_UARTS_TO_INIT 3
+#define HIGH_SPEED_CLK_MULT     24
+
+#endif /* _SOC_SNOWRIDGE_UART_H_ */
diff --git a/src/soc/intel/snowridge/common/upd_display.c b/src/soc/intel/snowridge/common/upd_display.c
new file mode 100644
index 0000000000..3c7f44bcef
--- /dev/null
+++ b/src/soc/intel/snowridge/common/upd_display.c
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <fsp/debug.h>
+#include <lib.h>
+
+#define DISPLAY_UPD(field) \
+	fsp_display_upd_value(#field, sizeof(old->field), old->field, new->field)
+
+void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd)
+{
+	const FSP_M_CONFIG *old = &fspm_old_upd->FspmConfig;
+	const FSP_M_CONFIG *new = &fspm_new_upd->FspmConfig;
+
+	printk(BIOS_SPEW, "UPD values for FspMemoryInit:\n");
+
+	DISPLAY_UPD(PcdEnableBiosSsaRMT);
+	DISPLAY_UPD(PcdEnableBiosSsaRMTonFCB);
+	DISPLAY_UPD(PcdBiosSsaPerBitMargining);
+	DISPLAY_UPD(PcdBiosSsaDisplayTables);
+	DISPLAY_UPD(PcdBiosSsaPerDisplayPlots);
+	DISPLAY_UPD(PcdBiosSsaLoopCount);
+	DISPLAY_UPD(PcdBiosSsaBacksideMargining);
+	DISPLAY_UPD(PcdBiosSsaEarlyReadIdMargining);
+	DISPLAY_UPD(PcdBiosSsaStepSizeOverride);
+	DISPLAY_UPD(PcdBiosSsaRxDqs);
+	DISPLAY_UPD(PcdBiosSsaRxVref);
+	DISPLAY_UPD(PcdBiosSsaTxDq);
+	DISPLAY_UPD(PcdBiosSsaTxVref);
+	DISPLAY_UPD(PcdBiosSsaCmdAll);
+	DISPLAY_UPD(PcdBiosSsaCmdVref);
+	DISPLAY_UPD(PcdBiosSsaCtlAll);
+	DISPLAY_UPD(PcdBiosSsaEridDelay);
+	DISPLAY_UPD(PcdBiosSsaEridVref);
+	DISPLAY_UPD(PcdBiosSsaDebugMessages);
+	DISPLAY_UPD(PcdEccSupport);
+	DISPLAY_UPD(PcdFastBoot);
+	DISPLAY_UPD(PcdMemTest);
+	DISPLAY_UPD(PcdMemTurnaroundOpt);
+	DISPLAY_UPD(PcdDdrFreq);
+	DISPLAY_UPD(PcdCommandTiming);
+	DISPLAY_UPD(PcdCustomRefreshRate);
+	DISPLAY_UPD(PcdTsegSize);
+	DISPLAY_UPD(PcdHsuartDevice);
+	DISPLAY_UPD(PcdHeciCommunication);
+	DISPLAY_UPD(PcdVtdSupport);
+	DISPLAY_UPD(PcdPchUsb3Port);
+	DISPLAY_UPD(PcdPchUsb2Port);
+	DISPLAY_UPD(PcdPchUsb3PortOc);
+	DISPLAY_UPD(PcdPchUsb2PortOc);
+	DISPLAY_UPD(PcdUsb2PeTxiSet);
+	DISPLAY_UPD(PcdUsb2TxiSet);
+	DISPLAY_UPD(PcdUsb2PreDeEmp);
+	DISPLAY_UPD(PcdUsb2PreEmpHalfBit);
+	DISPLAY_UPD(PcdIIOPciePortBifurcation);
+	DISPLAY_UPD(PcdIIoPcieRLinkDeEmphasis);
+	DISPLAY_UPD(PcdIIoPciePort1ADeEmphasis);
+	DISPLAY_UPD(PcdIIoPciePort1BDeEmphasis);
+	DISPLAY_UPD(PcdIIoPciePort1CDeEmphasis);
+	DISPLAY_UPD(PcdIIoPciePort1DDeEmphasis);
+	DISPLAY_UPD(PcdIIoPcieLinkSpeedRLink);
+	DISPLAY_UPD(PcdIIoPciePort1ALinkSpeed);
+	DISPLAY_UPD(PcdIIoPciePort1BLinkSpeed);
+	DISPLAY_UPD(PcdIIoPciePort1CLinkSpeed);
+	DISPLAY_UPD(PcdIIoPciePort1DLinkSpeed);
+	DISPLAY_UPD(PcdIIoPcieRLinkAspm);
+	DISPLAY_UPD(PcdIIoPciePort1AAspm);
+	DISPLAY_UPD(PcdIIoPciePort1BAspm);
+	DISPLAY_UPD(PcdIIoPciePort1CAspm);
+	DISPLAY_UPD(PcdIIoPciePort1DAspm);
+	DISPLAY_UPD(PcdBifurcationPcie0);
+	DISPLAY_UPD(PcdBifurcationPcie2);
+	DISPLAY_UPD(PcdMemoryThermalThrottling);
+	DISPLAY_UPD(PcdFiaMuxOverride);
+	DISPLAY_UPD(FiaMuxCfgInvalidate);
+	DISPLAY_UPD(PcdPchTraceHubMode);
+	DISPLAY_UPD(PcdPchTraceHubMemReg0Size);
+	DISPLAY_UPD(PcdPchTraceHubMemReg1Size);
+	DISPLAY_UPD(PcdFiaLaneConfigPtr);
+	DISPLAY_UPD(PcdKtiBufferPtr);
+	DISPLAY_UPD(PcdMemSpdPtr);
+
+	hexdump(fspm_new_upd, sizeof(*fspm_new_upd));
+}
+
+void soc_display_fsps_upd_params(const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd)
+{
+	const FSP_S_CONFIG *old = &fsps_old_upd->FspsConfig;
+	const FSP_S_CONFIG *new = &fsps_new_upd->FspsConfig;
+
+	printk(BIOS_SPEW, "UPD values for FspSiliconInit:\n");
+
+	DISPLAY_UPD(PcdCpuMicrocodePatchBase);
+	DISPLAY_UPD(PcdCpuMicrocodePatchSize);
+	DISPLAY_UPD(PcdEnableSATA);
+	DISPLAY_UPD(PcdEmmc);
+	DISPLAY_UPD(PcdEmmcHS400Support);
+	DISPLAY_UPD(PcdPcieRootPort0LinkSpeed);
+	DISPLAY_UPD(PcdPcieRootPort1LinkSpeed);
+	DISPLAY_UPD(PcdPcieRootPort2LinkSpeed);
+	DISPLAY_UPD(PcdPcieRootPort3LinkSpeed);
+	DISPLAY_UPD(PcdPcieRootPort8LinkSpeed);
+	DISPLAY_UPD(PcdPcieRootPort9LinkSpeed);
+	DISPLAY_UPD(PcdPcieRootPort10LinkSpeed);
+	DISPLAY_UPD(PcdPcieRootPort11LinkSpeed);
+	DISPLAY_UPD(PcdPcieRootPort0Aspm);
+	DISPLAY_UPD(PcdPcieRootPort1Aspm);
+	DISPLAY_UPD(PcdPcieRootPort2Aspm);
+	DISPLAY_UPD(PcdPcieRootPort3Aspm);
+	DISPLAY_UPD(PcdPcieRootPort8Aspm);
+	DISPLAY_UPD(PcdPcieRootPort9Aspm);
+	DISPLAY_UPD(PcdPcieRootPort10Aspm);
+	DISPLAY_UPD(PcdPcieRootPort11Aspm);
+	DISPLAY_UPD(PcdPcieRootPort0ConnectionType);
+	DISPLAY_UPD(PcdPcieRootPort1ConnectionType);
+	DISPLAY_UPD(PcdPcieRootPort2ConnectionType);
+	DISPLAY_UPD(PcdPcieRootPort3ConnectionType);
+	DISPLAY_UPD(PcdPcieRootPort8ConnectionType);
+	DISPLAY_UPD(PcdPcieRootPort9ConnectionType);
+	DISPLAY_UPD(PcdPcieRootPort10ConnectionType);
+	DISPLAY_UPD(PcdPcieRootPort11ConnectionType);
+	DISPLAY_UPD(PcdPcieRootPort0HotPlug);
+	DISPLAY_UPD(PcdPcieRootPort1HotPlug);
+	DISPLAY_UPD(PcdPcieRootPort2HotPlug);
+	DISPLAY_UPD(PcdPcieRootPort3HotPlug);
+	DISPLAY_UPD(PcdPcieRootPort8HotPlug);
+	DISPLAY_UPD(PcdPcieRootPort9HotPlug);
+	DISPLAY_UPD(PcdPcieRootPort10HotPlug);
+	DISPLAY_UPD(PcdPcieRootPort11HotPlug);
+	DISPLAY_UPD(PcdEMMCDLLConfigPtr);
+
+	hexdump(fsps_new_upd, sizeof(*fsps_new_upd));
+}