soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

This change adds support for Intel Atom Processors P5300, P5700
product families (known as Snow Ridge NS and Snow Ridge NX).

Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Tested-by: Vasiliy Khoruzhick <vasilykh@arista.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>

3 files changed, 120 insertions, 0 deletions

diff --git a/src/soc/intel/snowridge/bootblock/bootblock.c b/src/soc/intel/snowridge/bootblock/bootblock.c
new file mode 100644
index 0000000000..8e6c0def99
--- /dev/null
+++ b/src/soc/intel/snowridge/bootblock/bootblock.c
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/tco.h>
+#include <soc/iomap.h>
+
+#include <FsptUpd.h>
+
+#include "bootblock.h"
+
+const FSPT_UPD temp_ram_init_params = {
+	.FspUpdHeader = {
+		.Signature = 0x545F445055434F53ULL,
+		.Revision = 1,
+		.Reserved = {0},
+	},
+	.FsptCoreUpd = {
+		.MicrocodeRegionBase = 0,
+		.MicrocodeRegionLength = 0,
+		.CodeRegionBase = 0xffe00000,
+		.CodeRegionLength = 0x200000,
+		.Reserved1 = {0},
+	},
+	.ReservedTempRamInitUpd = {0},
+	.UnusedUpdSpace0 = {0},
+	.UpdTerminator = 0x55AA,
+};
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+	bootblock_main_with_basetime(base_timestamp);
+}
+
+void bootblock_soc_early_init(void)
+{
+	if (CONFIG(DRIVERS_UART))
+		early_uart_init();
+}
+
+void bootblock_soc_init(void)
+{
+	if (CONFIG(BOOTBLOCK_CONSOLE))
+		printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
+
+	if (CONFIG(FSP_CAR))
+		report_fspt_output();
+
+	tco_configure();
+	tco_reset_status();
+
+	fast_spi_early_init(SPI_BASE_ADDRESS);
+}
diff --git a/src/soc/intel/snowridge/bootblock/bootblock.h b/src/soc/intel/snowridge/bootblock/bootblock.h
new file mode 100644
index 0000000000..2cc732085a
--- /dev/null
+++ b/src/soc/intel/snowridge/bootblock/bootblock.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_SNOWRIDGE_BOOTBLOCK_H_
+#define _SOC_SNOWRIDGE_BOOTBLOCK_H_
+
+void early_uart_init(void);
+
+void early_tco_init(void);
+
+#endif // _SOC_SNOWRIDGE_BOOTBLOCK_H_
diff --git a/src/soc/intel/snowridge/bootblock/early_uart_init.c b/src/soc/intel/snowridge/bootblock/early_uart_init.c
new file mode 100644
index 0000000000..9f56ceba01
--- /dev/null
+++ b/src/soc/intel/snowridge/bootblock/early_uart_init.c
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <stdint.h>
+
+#include "../common/uart8250mem.h"
+#include "bootblock.h"
+
+static void pci_early_hsuart_device_enable(uint8_t func, uint16_t io_base)
+{
+	register uint16_t cmd_stat_reg;
+
+	pci_or_config32(PCH_DEV_UART(func), UART_IOBA, io_base);
+
+	/**
+	 * Enable memory/io space and allow to initiate a transaction as a master.
+	 */
+	cmd_stat_reg = pci_read_config16(PCH_DEV_UART(func), PCI_COMMAND);
+	cmd_stat_reg |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+
+#if CONFIG_CONSOLE_UART_BASE_ADDRESS != 0
+	/* Decode MMIO at MEMBA (BAR1). */
+	pci_write_config32(PCH_DEV_UART(func), UART_MEMBA,
+			   CONFIG_CONSOLE_UART_BASE_ADDRESS + SIZE_OF_HSUART_RES * func);
+	cmd_stat_reg |= PCI_COMMAND_MEMORY;
+#endif
+
+	pci_write_config16(PCH_DEV_UART(func), PCI_COMMAND, cmd_stat_reg);
+
+#if CONFIG_TTYS0_BAUD > 115200
+#if CONFIG_CONSOLE_UART_BASE_ADDRESS && CONFIG(ECAM_MMCONF_SUPPORT)
+#define UCMR_OFFSET 0x34
+	/**
+	 * Change UART baseclock to 24 x 1.8432MHz -> 44.2368MHz, use
+	 * `HIGH_SPEED_CLK_MULT` (24) times faster base clock.
+	 */
+	write32p(CONFIG_CONSOLE_UART_BASE_ADDRESS + UCMR_OFFSET,
+		 read32p(CONFIG_CONSOLE_UART_BASE_ADDRESS + UCMR_OFFSET) * HIGH_SPEED_CLK_MULT);
+#else
+#error MMIO access is required for baudrates above 115200.
+#endif
+#endif
+}
+
+void early_uart_init(void)
+{
+	static const uint16_t legacy_uart_io_port_tab[] = {0x3F8, 0x2F8, 0x3E8, 0x2E8};
+	register int i;
+
+	for (i = SNOWRIDGE_UARTS_TO_INIT - 1; i >= 0; --i) {
+		pci_early_hsuart_device_enable(i, legacy_uart_io_port_tab[i]);
+	}
+}