soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

This change adds support for Intel Atom Processors P5300, P5700
product families (known as Snow Ridge NS and Snow Ridge NX).

Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Tested-by: Vasiliy Khoruzhick <vasilykh@arista.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>

1 files changed, 62 insertions, 0 deletions

diff --git a/src/soc/intel/snowridge/Makefile.mk b/src/soc/intel/snowridge/Makefile.mk
new file mode 100644
index 0000000000..07f39231f0
--- /dev/null
+++ b/src/soc/intel/snowridge/Makefile.mk
@@ -0,0 +1,62 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ifeq ($(CONFIG_SOC_INTEL_SNOWRIDGE),y)
+
+subdirs-y += ../../../cpu/intel/microcode
+subdirs-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += ../../../cpu/intel/turbo
+
+all-$(CONFIG_HIGH_SPEED_UART) += common/uart8250mem.c
+all-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += common/gpio.c
+all-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += common/pmclib.c
+all-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI) += common/spi.c
+
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += bootblock/bootblock.c
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += bootblock/early_uart_init.c
+
+romstage-y += ../../../cpu/intel/car/romstage.c
+romstage-y += common/fsp_hob.c
+romstage-y += common/kti_cache.c
+romstage-y += romstage/gpio_snr.c
+romstage-y += romstage/romstage.c
+romstage-$(CONFIG_DISPLAY_HOBS) += common/hob_display.c
+romstage-$(CONFIG_DISPLAY_UPD_DATA) += common/upd_display.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += common/reset.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_SERVER) += common/systemagent_early.c
+
+ramstage-y += common/fsp_hob.c
+ramstage-y += common/kti_cache.c
+ramstage-y += chip.c
+ramstage-y += finalize.c
+ramstage-$(CONFIG_DISPLAY_HOBS) += common/hob_display.c
+ramstage-$(CONFIG_DISPLAY_UPD_DATA) += common/upd_display.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += common/reset.c
+ramstage-$(CONFIG_PCI) += dlb.c
+ramstage-$(CONFIG_PCI) += heci.c
+ramstage-$(CONFIG_PCI) += lpc.c
+ramstage-$(CONFIG_PCI) += nis.c
+ramstage-$(CONFIG_PCI) += pcie_rp.c
+ramstage-$(CONFIG_PCI) += qat.c
+ramstage-$(CONFIG_PCI) += sata.c
+ramstage-$(CONFIG_PCI) += sriov.c
+ramstage-$(CONFIG_PCI) += systemagent.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += cpu.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA_SERVER) += common/systemagent_early.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown.c
+
+smm-$(CONFIG_ARCH_RAMSTAGE_X86_32) += smihandler.c
+smm-$(CONFIG_HIGH_SPEED_UART) += common/uart8250mem.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += common/gpio.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += common/pmclib.c
+smm-$(CONFIG_SPI_FLASH_SMM) += common/spi.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/snowridge/include/
+
+## Set FSP binary blobs memory location
+
+$(call strip_quotes,$(CONFIG_FSP_T_CBFS))-position := $(CONFIG_FSP_T_LOCATION) --xip
+$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-position := $(CONFIG_FSP_M_ADDR) --xip
+$(call strip_quotes,$(CONFIG_FSP_S_CBFS))-position := $(CONFIG_FSP_S_ADDR) --xip
+
+endif ## CONFIG_SOC_INTEL_SNOWRIDGE