diff options
| author | Christian Walter <christian.walter@9elements.com> | 2019-05-28 10:37:24 +0200 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-06-06 11:32:52 +0000 |
| commit | f97232236891bc8f5c816a96c98807a0f2449234 (patch) | |
| tree | d837ce5e4798e39b9b5df28a265f4ad6141200df /src/soc/intel/skylake | |
| parent | fa36c6c3eed187f3ebc912eede900c8889df481d (diff) | |
src/soc/intel/common/smbios: Add addtional infos to dimm_info
Add ECC Support and VDD Voltage to dimm_info struct. Now Bus Width
and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry.
Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33031
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 04c369beb8..2819c6f260 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -114,6 +114,7 @@ static void save_dimm_info(void) ddr_type = MEMORY_TYPE_UNKNOWN; break; } + u8 memProfNum = memory_info_hob->MemoryProfile; /* Populate the DIMM information */ dimm_info_fill(dest_dimm, @@ -126,7 +127,9 @@ static void save_dimm_info(void) (const char *)src_dimm->ModulePartNum, sizeof(src_dimm->ModulePartNum), src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } |