diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2024-08-01 11:37:24 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-10-02 19:45:05 +0000 |
| commit | eee5c10c945c519710670da6bed84f612e330a98 (patch) | |
| tree | 1f6158e1ea24053b5b200bf9ab023300640ded2c /src/soc/intel/skylake | |
| parent | b90fac1cfe2fc858e60b6875752ea9dc69b72850 (diff) | |
soc/intel/cannonlake,skylake: Fix locking SMRAM
Intel TXT SINIT required the D_LCK bit set. Although coreboot
tries to set it, the bit ws still clear. The D_LCK bit has to be
set using I/O CF8/CFC cycle.
TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled
Change-Id: I03aff482b53ab7b0bcaccf18e47ad4c22b53583c
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5cf48eaded..057aece02d 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -164,14 +164,14 @@ static void per_cpu_smm_trigger(void) void smm_lock(void) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* * LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can - * make the SMM registers writable again. + * make the SMM registers writable again. D_LCK bit + * requires the PCI 0xcf8/0xcfc I/O access. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); + pci_io_write_config8(SA_DEVFN_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } static void vmx_configure(void *unused) |