diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-09-21 22:44:27 +0000 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-22 05:13:39 +0000 |
| commit | b13bd1efcf568bb220500ca94e4de097f3bed9ec (patch) | |
| tree | 498a45a955bbd97da0995a966e9356ae6236ce94 /src/soc/intel/skylake | |
| parent | 5bd4adf542abea433c98c72f7423762109412d4d (diff) | |
Revert "soc/intel: Refactor do_global_reset() function"
This reverts commit 77cc3267fc970c710299a164ecbc471f9287d719.
Reason for revert: Breaks quark and also needs breaking down into multiple CLs as commented by Nico on CB:45541
Change-Id: Idf4ca74158df15483856754ee24cc4472a8e09b0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/me.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/me.c | 19 | ||||
| -rw-r--r-- | src/soc/intel/skylake/reset.c | 27 |
3 files changed, 47 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 50cc087138..5dbcefe386 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -178,5 +178,6 @@ union me_hfsts6 { }; void intel_me_status(void); +int send_global_reset(void); #endif diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 1b222f313c..c37f6925c3 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -338,6 +338,25 @@ void intel_me_status(void) } } +int send_global_reset(void) +{ + int status = -1; + union me_hfsts1 hfs1; + + if (!is_cse_enabled()) + goto ret; + + /* Check ME operating mode */ + hfs1.data = me_read_config32(PCI_ME_HFSTS1); + if (hfs1.fields.operation_mode) + goto ret; + + /* ME should be in Normal Mode for this command */ + status = cse_request_global_reset(); +ret: + return status; +} + /* * This can't be put in intel_me_status because by the time control * reaches there, ME doesn't respond to GET_FW_VERSION command. diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index ecc052e6eb..1076ad2ffa 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -1,8 +1,35 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cf9_reset.h> #include <console/console.h> #include <fsp/util.h> +#include <intelblocks/pmclib.h> #include <soc/intel/common/reset.h> +#include <soc/me.h> +#include <soc/pm.h> + +static void do_force_global_reset(void) +{ + /* + * BIOS should ensure it does a global reset + * to reset both host and Intel ME by setting + * PCH PMC [B0:D31:F2 register offset 0xAC bit 20] + */ + pmc_global_reset_enable(true); + + /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port + * to global reset platform */ + do_full_reset(); +} + +void do_global_reset(void) +{ + if (!send_global_reset()) { + /* If ME unable to reset platform then + * force global reset using PMC CF9GR register*/ + do_force_global_reset(); + } +} void chipset_handle_reset(uint32_t status) { |