soc/intel/common/block: Move tco common functions into block/smbus

This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc
code into common/block/smbus.

BUG=b:78109109
BRANCH=NONE
TEST=Build and boot KBL/CNL/APL/ICL platform.

Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/26166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

5 files changed, 11 insertions, 88 deletions

diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 26ea56a93a..6403ed3ee7 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -2,8 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -27,6 +26,7 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/smbus.h>
+#include <intelblocks/tco.h>
 #include <soc/bootblock.h>
 #include <soc/iomap.h>
 #include <soc/p2sb.h>
@@ -43,7 +43,6 @@
 #define PCR_DMI_ACPIBDID	0x27B8
 #define PCR_DMI_PMBASEA		0x27AC
 #define PCR_DMI_PMBASEC		0x27B0
-#define PCR_DMI_TCOBASE		0x2778
 
 void bootblock_pch_early_init(void)
 {
@@ -112,37 +111,6 @@ static void soc_config_pwrmbase(void)
 		pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);
 }
 
-static void soc_config_tco(void)
-{
-	uint32_t reg32 = 0;
-	uint16_t tcobase;
-	uint16_t tcocnt;
-
-	/* Disable TCO in SMBUS Device first before changing Base Address */
-	reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);
-	reg32 &= ~TCO_EN;
-	pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
-
-	/* Program TCO Base */
-	pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDRESS);
-
-	/* Enable TCO in SMBUS */
-	pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN);
-
-	/*
-	 * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
-	 * to [SMBUS PCI offset 50h[15:5], 1].
-	 */
-	pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDRESS | (1 << 1));
-
-	/* Program TCO timer halt */
-	tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
-	tcobase &= ~0x1f;
-	tcocnt = inw(tcobase + TCO1_CNT);
-	tcocnt |= TCO_TMR_HLT;
-	outw(tcocnt, tcobase + TCO1_CNT);
-}
-
 static int pch_check_decode_enable(void)
 {
 	uint32_t dmi_control;
@@ -196,7 +164,7 @@ void pch_early_init(void)
 	soc_config_pwrmbase();
 
 	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
-	soc_config_tco();
+	tco_configure();
 
 	/* Program SMBUS_BASE_ADDRESS and Enable it */
 	smbus_common_init();
diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c
index 1fab92e2b0..de790fa461 100644
--- a/src/soc/intel/skylake/elog.c
+++ b/src/soc/intel/skylake/elog.c
@@ -373,7 +373,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
 
 	/* TCO Timeout */
 	if (ps->prev_sleep_state != ACPI_S3 &&
-	    ps->tco2_sts & TCO2_STS_SECOND_TO)
+	    ps->tco2_sts & TCO_STS_SECOND_TO)
 		elog_add_event(ELOG_TYPE_TCO_RESET);
 
 	/* Power Button Override */
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 47e3941531..f622edbde9 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -183,9 +183,6 @@ int acpi_sci_irq(void);
 /* Get base address PMC memory mapped registers. */
 uint8_t *pmc_mmio_regs(void);
 
-/* Get base address of TCO I/O registers. */
-uint16_t smbus_tco_regs(void);
-
 /* Set the DISB after DRAM init */
 void pmc_set_disb(void);
 
diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h
index aeaf1d9ea2..aad57aabb6 100644
--- a/src/soc/intel/skylake/include/soc/smbus.h
+++ b/src/soc/intel/skylake/include/soc/smbus.h
@@ -4,7 +4,7 @@
  * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
  * Copyright (C) 2009 coresystems GmbH
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2017 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,20 +22,14 @@
 /* PCI Configuration Space (D31:F3): SMBus */
 #define SMB_RCV_SLVA		0x09
 
-/* SMBUS TCO base address. */
-#define TCOBASE		0x50
-#define TCOCTL		0x54
-#define TCO_EN		(1 << 8)
-
 /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
 #define TCO1_STS			0x04
 #define  TCO_TIMEOUT			(1 << 3)
 #define TCO2_STS			0x06
-#define TCO2_STS_SECOND_TO		0x02
-#define TCO2_STS_BOOT			0x04
+#define  TCO_STS_SECOND_TO		0x02
 #define TCO1_CNT			0x08
-#define TCO_LOCK			(1 << 12)
-#define TCO_TMR_HLT			(1 << 11)
+#define  TCO_LOCK			(1 << 12)
+#define  TCO_TMR_HLT			(1 << 11)
 
 /* SMBus I/O bits. */
 #define SMBUS_SLAVE_ADDR	0x24
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 2e1d1713e1..335df53ddc 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -28,6 +28,7 @@
 #include <intelblocks/pmclib.h>
 #include <halt.h>
 #include <intelblocks/lpc_lib.h>
+#include <intelblocks/tco.h>
 #include <rules.h>
 #include <stdlib.h>
 #include <soc/gpe.h>
@@ -168,40 +169,6 @@ uint8_t *pmc_mmio_regs(void)
 	return (void *)(uintptr_t) reg32;
 }
 
-uint16_t smbus_tco_regs(void)
-{
-	uint16_t reg16;
-
-	reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
-
-	reg16 &= ~0x1f;
-
-	return reg16;
-}
-
-uint32_t soc_reset_tco_status(void)
-{
-	u16 tco1_sts;
-	u16 tco2_sts;
-	u16 tcobase;
-
-	tcobase = smbus_tco_regs();
-
-	/* TCO Status 2 register */
-	tco2_sts = inw(tcobase + TCO2_STS);
-	tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);
-	outw(tco2_sts, tcobase + TCO2_STS);
-
-	/* TCO Status 1 register */
-	tco1_sts = inw(tcobase + TCO1_STS);
-
-	/* Clear SECOND_TO_STS bit */
-	if (tco2_sts & TCO2_STS_SECOND_TO)
-		outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
-
-	return (tco2_sts << 16) | tco1_sts;
-}
-
 uintptr_t soc_read_pmc_base(void)
 {
 	return (uintptr_t) (pmc_mmio_regs());
@@ -285,13 +252,10 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
 
 void soc_fill_power_state(struct chipset_power_state *ps)
 {
-	uint16_t tcobase;
 	uint8_t *pmc;
 
-	tcobase = smbus_tco_regs();
-
-	ps->tco1_sts = inw(tcobase + TCO1_STS);
-	ps->tco2_sts = inw(tcobase + TCO2_STS);
+	ps->tco1_sts = tco_read_reg(TCO1_STS);
+	ps->tco2_sts = tco_read_reg(TCO2_STS);
 
 	printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
 	       ps->tco1_sts, ps->tco2_sts);