intel/fsp1_1: Move MRC cache pointers into `romstage_params`

These are part of a common concept and not SoC specific.

Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>

3 files changed, 6 insertions, 18 deletions

diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h
index 7406a3322e..5ea2190b8e 100644
--- a/src/soc/intel/skylake/include/soc/pei_data.h
+++ b/src/soc/intel/skylake/include/soc/pei_data.h
@@ -80,16 +80,7 @@ struct pei_data {
 	uint8_t dqs_map[2][8];
 	uint16_t RcompResistor[3];
 	uint16_t RcompTarget[5];
-	/* Data read from flash and passed into MRC */
-	const void *saved_data;
-	int saved_data_size;
 
-	/* Disable use of saved data (can be set by mainboard) */
-	int disable_saved_data;
-
-	/* Data from MRC that should be saved to flash */
-	void *data_to_save;
-	int data_to_save_size;
 	int mem_cfg_id;
 } __packed;
 
diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c
index 203a1d8e36..7d314a106f 100644
--- a/src/soc/intel/skylake/pei_data.c
+++ b/src/soc/intel/skylake/pei_data.c
@@ -33,16 +33,7 @@ static void ABI_X86 send_to_console(unsigned char b)
 
 void soc_fill_pei_data(struct pei_data *pei_data)
 {
-	const struct device *dev;
-	const struct soc_intel_skylake_config *config;
-
 	/* Set the parameters for MemoryInit */
-	dev = dev_find_slot(0, PCH_DEVFN_LPC);
-	config = dev->chip_info;
-
 	pei_data->pei_version = PEI_VERSION;
 	pei_data->tx_byte = &send_to_console;
-
-	/* Force a full memory train if RMT is enabled */
-	pei_data->disable_saved_data = config->Rmt;
 }
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 0501b04493..8ec08c2d0f 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -46,6 +46,12 @@ void soc_pre_ram_init(struct romstage_params *params)
 
 	/* Prepare to initialize memory */
 	soc_fill_pei_data(params->pei_data);
+
+	const struct device *const dev = pcidev_path_on_root(PCH_DEVFN_LPC);
+	const struct soc_intel_skylake_config *const config =
+		dev ? dev->chip_info : NULL;
+	/* Force a full memory train if RMT is enabled */
+	params->disable_saved_data = config && config->Rmt;
 }
 
 /* UPD parameters to be initialized before MemoryInit */