diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2018-01-30 09:51:38 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-01-31 09:55:59 +0000 |
| commit | 61e4e1ab6fffb05f9f18eeeaa1cf3959492e8a13 (patch) | |
| tree | 476c2ed500953f6f841ca160cedec76cb3be08dd /src/soc/intel/skylake | |
| parent | 00c0cd2c45d503716dfd7d37ebff6c6768712a52 (diff) | |
soc/intel/skylake: Fix common timer frequency
The calculation to set up the PM timer emulation is using an
incorrect common timer clock value that was copied from Apollolake.
According to the PDG Skylake and Kabylake clocks are derived from a
24MHz XTAL, not 19.2MHz like Apollolake.
Fixing this value results in the proper "correction value" to be
programmed into the PM timer emulation MSR that matches the raw value
that would be programmed by FSP. (if it were doing MpInit)
Old PM timer correction value: 0x2fba2e25
New PM timer correction value: 0x262e8b51
Change-Id: Ib2bb3cb1938ae34cfa7aef177bef6fc24da73335
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23509
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/cpu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 8073fcdded..cc76b19cd5 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -40,8 +40,8 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 -/* Common Timer Copy (CTC) frequency - 19.2MHz. */ -#define CTC_FREQ 19200000 +/* Common Timer Copy (CTC) frequency - 24MHz. */ +#define CTC_FREQ 24000000 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) |