diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2021-02-16 13:20:13 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-18 10:11:55 +0000 |
commit | 1999bc5d001aa57f18fa264d9101afc7174baf26 (patch) | |
tree | 66c61abfffa69bcaa591f5c17165349aa6b67720 /src/soc/intel/skylake | |
parent | c027ece821ed3f65f7c08fb0b6d9b707401dddc4 (diff) |
soc/intel/skylake: Move soc_fsp_load
Move this function into the compilation unit where it is called.
Change-Id: Ia4bdcd545827c2564430521a98246fc96bf0ba92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r-- | src/soc/intel/skylake/chip.c | 5 | ||||
-rw-r--r-- | src/soc/intel/skylake/cpu.c | 5 | ||||
-rw-r--r-- | src/soc/intel/skylake/include/soc/ramstage.h | 1 |
3 files changed, 5 insertions, 6 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 4f120bc19d..728b023c70 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -74,11 +74,6 @@ void soc_init_pre_device(void *chip_info) pcie_rp_update_devicetree(pch_lp_rp_groups); } -void soc_fsp_load(void) -{ - fsps_load(); -} - static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 307c849550..4cadb7f9ee 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -176,6 +176,11 @@ static void post_mp_init(void) printk(BIOS_CRIT, "CRITICAL ERROR: MP post init failed\n"); } +static void soc_fsp_load(void) +{ + fsps_load(); +} + static const struct mp_ops mp_ops = { /* * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h index f6a4b848bc..02d53a1e17 100644 --- a/src/soc/intel/skylake/include/soc/ramstage.h +++ b/src/soc/intel/skylake/include/soc/ramstage.h @@ -13,7 +13,6 @@ #define FSP_MEM_UPD FSP_M_CONFIG void mainboard_silicon_init_params(FSP_S_CONFIG *params); -void soc_fsp_load(void); void soc_init_pre_device(void *chip_info); void soc_irq_settings(FSP_SIL_UPD *params); const char *soc_acpi_name(const struct device *dev); |