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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-15 00:27:59 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-26 06:49:40 +0000
commitd5a45470c816bc8a8bdc43951c9e4c4a592b55d3 (patch)
treebe365703931ffba49c9ed2abbe9d6af85cc1759b /src/soc/intel/skylake
parent6267cc523b4a6f716060214d06a8226412a65837 (diff)
soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead of relying on the devicetree option `speed_shift_enable`, that is going to be dropped. Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/acpi.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 275e77df1a..637092be97 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -35,6 +35,8 @@
#include "chip.h"
+#define CPUID_6_EAX_ISST (1 << 7)
+
/*
* List of suported C-states in this processor.
*/
@@ -379,7 +381,7 @@ void generate_cpu_entries(const struct device *device)
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
numcpus, cores_per_package);
- if (config->speed_shift_enable) {
+ if (cpuid_eax(6) & CPUID_6_EAX_ISST) {
struct cppc_config cppc_config;
cpu_init_cppc_config(&cppc_config, 2 /* version 2 */);
acpigen_write_CPPC_package(&cppc_config);
@@ -405,7 +407,7 @@ void generate_cpu_entries(const struct device *device)
cores_per_package);
}
- if (config->speed_shift_enable)
+ if (cpuid_eax(6) & CPUID_6_EAX_ISST)
acpigen_write_CPPC_method();
acpigen_pop_len();