soc/intel: Replace uses of dev_find_slot()

To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.

Replace this with method that relies on bus topology
that walks the root bus only.

Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

9 files changed, 23 insertions, 23 deletions

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index bd944dac16..910db970f6 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -174,7 +174,7 @@ static int get_cores_per_package(void)
 
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
 
 	/* Set unknown wake source */
@@ -561,7 +561,7 @@ void generate_cpu_entries(struct device *device)
 
 static unsigned long acpi_fill_dmar(unsigned long current)
 {
-	struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+	struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
 	const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;
 
@@ -584,7 +584,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
 		acpi_dmar_rmrr_fixup(tmp, current);
 	}
 
-	struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB);
+	struct device *const p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB);
 	const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
 	const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1;
 
@@ -695,7 +695,7 @@ void southbridge_inject_dsdt(struct device *device)
 /* Save wake source information for calculating ACPI _SWS values */
 int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
 {
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
 	struct chipset_power_state *ps;
 	static uint32_t gpe0_sts[GPE0_REG_MAX];
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 6f90178f52..7f28340ba4 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -92,7 +92,7 @@ struct chip_operations soc_intel_skylake_ops = {
 /* UPD parameters to be initialized before SiliconInit */
 void soc_silicon_init_params(SILICON_INIT_UPD *params)
 {
-	struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
 	int i;
 
@@ -152,7 +152,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->ScsSdCardEnabled = config->ScsSdCardEnabled;
 
 	/* Enable ISH if device is on */
-	dev = dev_find_slot(0, PCH_DEVFN_ISH);
+	dev = pcidev_path_on_root(PCH_DEVFN_ISH);
 	if (dev)
 		params->IshEnable = dev->enabled;
 	else
@@ -219,11 +219,11 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 		fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
 
 	/* Show SPI controller if enabled in devicetree.cb */
-	dev = dev_find_slot(0, PCH_DEVFN_SPI);
+	dev = pcidev_path_on_root(PCH_DEVFN_SPI);
 	params->ShowSpiController = dev->enabled;
 
 	/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
 	if (!xdci_can_enable())
 		dev->enabled = 0;
 	params->XdciEnable = dev->enabled;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index d179598699..08f5d79349 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -102,7 +102,7 @@ static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group,
 
 	for (group = 0; group < pci_groups; group++) {
 		devfn0 = pcie_rp_group[group].devfn;
-		func0 = dev_find_slot(0, devfn0);
+		func0 = pcidev_path_on_root(devfn0);
 		if (func0 == NULL)
 			continue;
 
@@ -119,7 +119,7 @@ static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group,
 		 */
 		for (i = 1; i < pcie_rp_group[group].func_count;
 				i++, devfn += inc) {
-			struct device *dev = dev_find_slot(0, devfn);
+			struct device *dev = pcidev_path_on_root(devfn);
 			if (dev == NULL || !dev->enabled)
 				continue;
 
@@ -354,7 +354,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	}
 
 	/* If ISH is enabled, enable ISH elements */
-	dev = dev_find_slot(0, PCH_DEVFN_ISH);
+	dev = pcidev_path_on_root(PCH_DEVFN_ISH);
 	if (dev)
 		params->PchIshEnable = dev->enabled;
 	else
@@ -433,11 +433,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
 
 	/* Show SPI controller if enabled in devicetree.cb */
-	dev = dev_find_slot(0, PCH_DEVFN_SPI);
+	dev = pcidev_path_on_root(PCH_DEVFN_SPI);
 	params->ShowSpiController = dev->enabled;
 
 	/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
 	if (!xdci_can_enable())
 		dev->enabled = 0;
 	params->XdciEnable = dev->enabled;
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index d59c80008b..5acaaebc5a 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -24,8 +24,8 @@
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
-#define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _SA_DEV(slot)		pcidev_path_on_root(_SA_DEVFN(slot))
+#define _PCH_DEV(slot, func)	pcidev_path_on_root(_PCH_DEVFN(slot, func))
 #else
 #define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
@@ -39,7 +39,7 @@
 
 #define SA_DEV_SLOT_PEG		0x01
 #define  SA_DEVFN_PEG(func)	PCI_DEVFN(SA_DEV_SLOT_PEG, func)
-#define  SA_DEV_PEG(func)	dev_find_slot(0, SA_DEVFN_PEG(func))
+#define  SA_DEV_PEG(func)	pcidev_path_on_root(SA_DEVFN_PEG(func))
 #define  SA_DEV_PEG0		SA_DEV_PEG(0)
 #define  SA_DEV_PEG1		SA_DEV_PEG(1)
 #define  SA_DEV_PEG2		SA_DEV_PEG(2)
diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c
index d10ca74f1e..03cdb071ce 100644
--- a/src/soc/intel/skylake/irq.c
+++ b/src/soc/intel/skylake/irq.c
@@ -223,7 +223,7 @@ void soc_irq_settings(FSP_SIL_UPD *params)
 
 	uint32_t i, intdeventry;
 	u8 irq_config[PCH_MAX_IRQ_CONFIG];
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
 
 	/* Get Device Int Count */
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 7d0dc0adb8..9732aa1617 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -178,7 +178,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 	DEVTREE_CONST struct soc_intel_skylake_config *config;
 
 	/* Look up the device in devicetree */
-	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
+	DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
 		return;
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 29c4774dc1..2bbab475af 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -57,7 +57,7 @@ void soc_memory_init_params(struct romstage_params *params,
 	const struct soc_intel_skylake_config *config;
 
 	/* Set the parameters for MemoryInit */
-	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+	dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
 	config = dev->chip_info;
 
 	/*
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index fafa343780..6884a324a8 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -301,7 +301,7 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
 {
 	const struct device *dev;
 
-	dev = dev_find_slot(0, SA_DEVFN_IGD);
+	dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	if (!dev || !dev->enabled) {
 		/*
 		 * If iGPU is disabled or not defined in the devicetree.cb,
@@ -331,7 +331,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
 
-	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+	dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
 	config = dev->chip_info;
 
 	soc_memory_init_params(m_cfg, config);
diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c
index 71a9bee1e0..00f620ff14 100644
--- a/src/soc/intel/skylake/romstage/systemagent.c
+++ b/src/soc/intel/skylake/romstage/systemagent.c
@@ -26,8 +26,8 @@
 
 static void systemagent_vtd_init(void)
 {
-	const struct device *const root_dev = dev_find_slot(0, SA_DEVFN_ROOT);
-	const struct device *const igd_dev = dev_find_slot(0, SA_DEVFN_IGD);
+	const struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+	const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	const struct soc_intel_skylake_config *config = NULL;
 
 	if (root_dev)