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| author | Mike Banon <mikebdp2@gmail.com> | 2020-11-21 21:58:50 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-11-23 19:18:03 +0000 |
| commit | 1e6a227f1001825f3a948b0734fe60dc0313a88c (patch) | |
| tree | b9e9e537493234973195b7f642279890282dfc18 /src/soc/intel/skylake | |
| parent | 58d0336ef382cf299923777e269d11fd9fadcfa1 (diff) | |
nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices
Follow the example of newer AMD code for Stoneyridge and Picasso.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/skylake')
0 files changed, 0 insertions, 0 deletions