spi: Clean up SPI flash driver interface

RW flag was added to spi_slave structure to get around a requirement on
some AMD flash controllers that need to group together all spi volatile
operations (write/erase). This rw flag is not a property or attribute of
the SPI slave or controller. Thus, instead of saving it in spi_slave
structure, clean up the SPI flash driver interface. This allows
chipsets/mainboards (that require volatile operations to be grouped) to
indicate beginning and end of such grouped operations.

New user APIs are added to allow users to perform probe, read, write,
erase, volatile group begin and end operations. Callbacks defined in
spi_flash structure are expected to be used only by the SPI flash
driver. Any chipset that requires grouping of volatile operations can
select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and
define callbacks for chipset_volatile_group_{begin,end}.

spi_claim_bus/spi_release_bus calls have been removed from the SPI flash
chip drivers which end up calling do_spi_flash_cmd since it already has
required calls for claiming and releasing SPI bus before performing a
read/write operation.

BUG=None
BRANCH=None
TEST=Compiles successfully.

Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17462
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

3 files changed, 18 insertions, 19 deletions

diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index 56c7c69527..5a715a4011 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -18,12 +18,12 @@
 #include <stdlib.h>
 #include <string.h>
 #include <bootstate.h>
-#include <spi_flash.h>
 #include <timer.h>
 #include <soc/flash_controller.h>
 #include <soc/intel/common/spi.h>
 #include <soc/pci_devs.h>
 #include <soc/spi.h>
+#include <spi-generic.h>
 
 static inline uint16_t spi_read_hsfs(pch_spi_regs * const regs)
 {
@@ -181,7 +181,7 @@ void spi_release_bus(struct spi_slave *slave)
 	/* Handled by PCH automatically. */
 }
 
-int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
+int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len)
 {
 	u32 start, end, erase_size;
 	int ret = 0;
@@ -192,8 +192,6 @@ int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
 		return -1;
 	}
 
-	flash->spi->rw = SPI_WRITE_FLAG;
-
 	start = offset;
 	end = start + len;
 
@@ -231,7 +229,8 @@ static void pch_read_data(uint8_t *data, int len)
 	}
 }
 
-int pch_hwseq_read(struct spi_flash *flash, u32 addr, size_t len, void *buf)
+int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
+		void *buf)
 {
 	uint8_t block_len;
 
@@ -292,8 +291,8 @@ static void pch_fill_data(const uint8_t *data, int len)
 		writel_(temp32, (uint8_t *)spi_bar->fdata + (i - (i % 4)));
 }
 
-int pch_hwseq_write(struct spi_flash *flash,
-			   u32 addr, size_t len, const void *buf)
+int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
+		const void *buf)
 {
 	uint8_t block_len;
 	uint32_t start = addr;
@@ -330,7 +329,7 @@ int pch_hwseq_write(struct spi_flash *flash,
 	return 0;
 }
 
-int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg)
+int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg)
 {
 	size_t block_len = SPI_READ_STATUS_LENGTH;
 	const int timeout_ms = 6;
@@ -358,10 +357,10 @@ static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi)
 	flash->spi = spi;
 	flash->name = "Opaque HW-sequencing";
 
-	flash->write = pch_hwseq_write;
-	flash->erase = pch_hwseq_erase;
-	flash->read = pch_hwseq_read;
-	flash->status = pch_hwseq_read_status;
+	flash->internal_write = pch_hwseq_write;
+	flash->internal_erase = pch_hwseq_erase;
+	flash->internal_read = pch_hwseq_read;
+	flash->internal_status = pch_hwseq_read_status;
 
 	/* The hardware sequencing supports 4KiB or 64KiB erase. Use 4KiB. */
 	flash->sector_size = 4*KiB;
diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h
index 49d60b0cd4..00500670fe 100644
--- a/src/soc/intel/skylake/include/soc/flash_controller.h
+++ b/src/soc/intel/skylake/include/soc/flash_controller.h
@@ -21,13 +21,12 @@
 #include <console/console.h>
 #include <spi_flash.h>
 
-int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len);
-int pch_hwseq_write(struct spi_flash *flash,
-			   u32 addr, size_t len, const void *buf);
-
-int pch_hwseq_read(struct spi_flash *flash,
-			  u32 addr, size_t len, void *buf);
-int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg);
+int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len);
+int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
+		const void *buf);
+int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
+		void *buf);
+int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg);
 
 
 #if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c
index db69cbeab7..16224046d7 100644
--- a/src/soc/intel/skylake/romstage/spi.c
+++ b/src/soc/intel/skylake/romstage/spi.c
@@ -16,6 +16,7 @@
 
 #include <soc/flash_controller.h>
 #include <soc/romstage.h>
+#include <spi-generic.h>
 
 /*
  * Minimal set of commands to read WPSR from SPI.