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authorWim Vervoorn <wvervoorn@eltan.com>2020-02-03 15:32:54 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-18 16:27:01 +0000
commit5f2adfe1a30627b0a416418a0cac59b9104bfbef (patch)
tree240eece566616dcd66e390b1674e4018aede5205 /src/soc/intel/skylake
parent53a9e418913df9becc5a42a8e4e33466db528e1b (diff)
soc/intel/skylake: Control fixed IO decode from devicetree
The current implementation doesn't allow custom values for the LPC IO decodes and IO enables. Add the lpc_ioe and lpc_iod values. If they are not zero, they will be used instead of the current handling for COMA and COMB. BUG=N/A TEST=tested on facebook monolith Change-Id: Iad7bb0e44739e8d656a542c79af7f98a4e9bde69 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38748 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c13
-rw-r--r--src/soc/intel/skylake/chip.h4
2 files changed, 14 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index d5d3aedc3d..b9a5633026 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -127,9 +127,16 @@ void pch_early_iorange_init(void)
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
LPC_IOE_EC_62_66;
- /* IO Decode Range */
- if (CONFIG(DRIVERS_UART_8250IO))
- lpc_io_setup_comm_a_b();
+ const config_t *config = config_of_soc();
+
+ if (config->lpc_ioe) {
+ io_enables = config->lpc_ioe & 0x3f0f;
+ lpc_set_fixed_io_ranges(config->lpc_iod, 0x1377);
+ } else {
+ /* IO Decode Range */
+ if (CONFIG(DRIVERS_UART_8250IO))
+ lpc_io_setup_comm_a_b();
+ }
/* IO Decode Enable */
if (pch_check_decode_enable() == 0) {
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 2c3d3a59c8..69b818bab9 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -79,6 +79,10 @@ struct soc_intel_skylake_config {
uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
+ /* LPC fixed enables and ranges */
+ uint16_t lpc_iod;
+ uint16_t lpc_ioe;
+
/* Generic IO decode ranges */
uint32_t gen1_dec;
uint32_t gen2_dec;