diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-09-10 15:51:17 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-09-12 04:28:20 +0000 |
| commit | 3eff037f8cbe99f72626c0f25c0989ea638599ef (patch) | |
| tree | d4db81b1d76e96e38e6862389e8d183319a8ca9d /src/soc/intel/skylake | |
| parent | b3426c03b4cf84af871c6d4c32afed2086f3fd1a (diff) | |
soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API
This patch removes dedicated function call to make TSEG region cache
from soc and refers to postcar_enable_tseg_cache().
BUG=b:140008206
Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/memmap.c | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 4c3c58a12d..29f2517468 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -296,8 +296,6 @@ void *cbmem_top(void) void fill_postcar_frame(struct postcar_frame *pcf) { uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; /* * We need to make sure ramstage will be run cached. At this @@ -310,14 +308,7 @@ void fill_postcar_frame(struct postcar_frame *pcf) top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } #endif |