diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-09 18:55:58 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-10 21:25:53 +0000 |
| commit | 3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d (patch) | |
| tree | 7b5096ca1f81fecf70418020aba184e446f995e0 /src/soc/intel/skylake | |
| parent | 1895838e7a3807a6fce324f0dfed193a3821f6df (diff) | |
src: Fix typo
Change-Id: I689c5663ef59861f79b68220abd146144f7618de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/iomap.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 4c88ed55bf..26ea56a93a 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -124,7 +124,7 @@ static void soc_config_tco(void) pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); /* Program TCO Base */ - pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); + pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDRESS); /* Enable TCO in SMBUS */ pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN); @@ -133,7 +133,7 @@ static void soc_config_tco(void) * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] * to [SMBUS PCI offset 50h[15:5], 1]. */ - pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1)); + pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDRESS | (1 << 1)); /* Program TCO timer halt */ tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index f2fde715f7..475d79db71 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -87,7 +87,7 @@ #define ACPI_BASE_ADDRESS 0x1800 #define ACPI_BASE_SIZE 0x100 -#define TCO_BASE_ADDDRESS 0x400 +#define TCO_BASE_ADDRESS 0x400 #define TCO_BASE_SIZE 0x20 #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS |