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authorPatrick Rudolph <patrick.rudolph@9elements.com>2021-01-25 10:46:16 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-15 08:20:19 +0000
commitfc36e9fb0e81cf7b6b17a51f023d030b0ab117f9 (patch)
tree529343d48b2e0938484a9ffd948cd0c938d50e0e /src/soc/intel/skylake
parentaacbd66a8537fe4ec45109324caa89145e70c1bd (diff)
soc/intel/*: Move prmrr_core_configure
Move prmrr_core_configure before clearing MCEs. This is required for the following patch in order to update microcode after PRMRR has been configured, but before MCEs have been cleared. According to Document 565432 this should be no issue in regards to SGX activation. Change-Id: Id2808a3989adff493aaf4175cbeccd080efaaedf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/cpu.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 1647db4855..307c849550 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -97,6 +97,10 @@ static void configure_c_states(void)
/* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu)
{
+ /* Configure Core PRMRR for SGX. */
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
+ prmrr_core_configure();
+
/* Clear out pending MCEs */
/* TODO(adurbin): This should only be done on a cold boot. Also, some
* of these banks are core vs package scope. For now every CPU clears
@@ -126,10 +130,6 @@ void soc_core_init(struct device *cpu)
/* Enable Turbo */
enable_turbo();
-
- /* Configure Core PRMRR for SGX. */
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
- prmrr_core_configure();
}
static void per_cpu_smm_trigger(void)