diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2015-07-07 18:18:15 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-29 20:26:10 +0200 |
| commit | c33958310ef820162b2c8f31a10e89a8b7b76d3d (patch) | |
| tree | 4280ac2fcd6d17e3f7a842c35364410a06894060 /src/soc/intel/skylake | |
| parent | 8d8799a33aac86c2acdf94e0f0af3ef291748536 (diff) | |
Skylake: Fix microcode reload in bootblock cpu init
If Skylake microcode is being loaded from FIT, Skylake supports
the PRMRR/SGX feature. If this is supported the FIT microcode
load will set the msr (0x08b) with the patch ID one less than the
ID in the microcode binary. This results in microcode getting
reloaded again in the bootblock cpu init.
Avoid the microcode reload by checking for PRMRR support.
BUG=chrome-os-partner:42046
BRANCH=None
TEST=Built for glados and tested on RVP3
Change-Id: I06e59f5cad549098c7ba2dfa608cd94a0b3f0ae1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6242b9dea283149bd0c968af1ba186647d37162d
Original-Change-Id: Iea5a223aa625be3fc451e8ee5d3510f548b07f8b
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286054
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11052
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/cpu.c | 24 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/msr.h | 2 |
2 files changed, 24 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index d4506e592a..2e3e000aaa 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -178,11 +178,33 @@ static void check_for_clean_reset(void) soft_reset(); } +static int need_microcode_update(void) +{ + /* If PRMRR/SGX is supported the FIT microcode load step will set + * msr 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. Check for this feature and avoid reloading the + * same microcode during early cpu initialization. + */ + msr = rdmsr(MTRRcap_MSR); + return (msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1); +} + static void bootblock_cpu_init(void) { + const struct microcode *patch; + u32 current_rev; + msr_t msr; + /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); check_for_clean_reset(); enable_rom_caching(); - intel_update_microcode_from_cbfs(); + + patch = intel_microcode_find(); + + current_rev = read_microcode_rev(); + + if (need_microcode_update()) + intel_update_microcode_from_cbfs(); } diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index b857dbe85e..390375703e 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -105,6 +105,6 @@ /* MTRRcap_MSR bits */ #define SMRR_SUPPORTED (1<<11) -#define EMRR_SUPPORTED (1<<12) +#define PRMRR_SUPPORTED (1<<12) #endif |