diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-08-25 11:54:10 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-25 18:02:14 +0000 |
| commit | 84f428f740b7ad257729e2e68426fb5de06bde82 (patch) | |
| tree | dbc388162d51e74300810e79dfe7db4bab883a52 /src/soc/intel/skylake | |
| parent | b51f54b518bf17a1bfb678d3d14dcf0996d882d2 (diff) | |
soc/intel/skylake: Remove ABASE lock down programming
FSP is doing PMC ABASE lock inside Post PCI bus enumeration
NotifyPhase(). Hence remove ABASE Lock down programming
from coreboot.
TEST= Ensure GEN_PMCON_B offset 0xA4 bit 17, 18 is set.
Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/finalize.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index a793e9551c..2fb37caa9d 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -126,12 +126,6 @@ static void pch_finalize_script(void) tcocnt |= TCO_LOCK; outw(tcocnt, tcobase + TCO1_CNT); - /* Lock down ABASE and sleep stretching policy */ - dev = PCH_DEV_PMC; - reg32 = pci_read_config32(dev, GEN_PMCON_B); - reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); - pci_write_config32(dev, GEN_PMCON_B, reg32); - /* PMSYNC */ pmcbase = pmc_mmio_regs(); pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); @@ -141,7 +135,7 @@ static void pch_finalize_script(void) /* Display me status before we hide it */ intel_me_status(); - /* we should disable Heci1 based on the devicetree policy */ + dev = PCH_DEV_PMC; config = dev->chip_info; /* |