diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-01 08:47:51 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-11 21:06:53 +0000 |
| commit | 419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 (patch) | |
| tree | 8b5a5413e791e15d7e386c958b2a24899d8cddc2 /src/soc/intel/skylake | |
| parent | 603963e1ba4147ef31a72b94304708ab416e3b6a (diff) | |
src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.
Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/msr.h | 7 |
2 files changed, 2 insertions, 9 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 7a66ed0e33..cf039d5845 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -357,10 +357,10 @@ static void set_energy_perf_bias(u8 policy) return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); } diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 780f94fdc9..6da9325d87 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -24,13 +24,6 @@ #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_DELAY_VALUE 0x13 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 |