diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2017-01-18 14:31:59 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-20 17:18:48 +0100 |
| commit | 3c78eae369ff3f96dbc901ca6c258b3e5fea847e (patch) | |
| tree | c72275c54825a05d981df0f77c0a6b404812bed3 /src/soc/intel/skylake | |
| parent | cdb93a592274f4e8f423b5d27ecf25374e7dcd15 (diff) | |
google/eve: Adjust DPTF parameters
- Remove the 0mA entry for the charger performance table
- Slightly raise the passive limit for TSR2/TSR3 to 55C
BUG=chrome-os-partner:58666
TEST=manual testing on P1 system
Change-Id: I75c66afe04afbbdb64a45833eb938e57ff21b392
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18172
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
0 files changed, 0 insertions, 0 deletions