diff options
| author | pchandri <preetham.chandrian@intel.com> | 2015-09-09 17:22:09 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:18:09 +0100 |
| commit | 1d77c721d3ad661e1cdca19901830fb1fe75282f (patch) | |
| tree | 7515f65e8878dc921054b54a684b773653ccecbf /src/soc/intel/skylake | |
| parent | f16bb7cce3767756e76b98d4f71fe3fe517a698d (diff) | |
intel/kunimitsu FAB3: Configure LPC to Quiet Mode.
This patch configures the LPC to quiet mode and sets
enables CLKRUN so that LPC can be power gated.
BUG=chrome-os-partner:44993
BRANCH=none
TEST=Builds and Boots on fab3 kunimitsu.
Change-Id: I46ff21f75b70f54da3f12dcc56d61f84b436cd7d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: edd37df385bc013b62f26435267291acc0a9b9a4
Original-Change-Id: Ide0f9e91127aebb8ac027ee0a598608b50aa4278
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/305396
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Reviewed-on: http://review.coreboot.org/12153
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/lpc.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/lpc.c | 2 |
3 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 1f42927254..2ea20a0803 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -119,7 +119,7 @@ config SERIAL_CPU_INIT config SERIRQ_CONTINUOUS_MODE bool - default y + default n help If you set this option to y, the serial IRQ machine will be operated in continuous mode. diff --git a/src/soc/intel/skylake/include/soc/lpc.h b/src/soc/intel/skylake/include/soc/lpc.h index 4e826d7688..63ffa16d6e 100644 --- a/src/soc/intel/skylake/include/soc/lpc.h +++ b/src/soc/intel/skylake/include/soc/lpc.h @@ -54,4 +54,6 @@ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LGMR 0x98 /* LPC Generic Memory Range */ #define BIOS_CNTL 0xdc +#define PCCTL 0xE0 /* PCI Clock Control */ +#define CLKRUN_EN (1 << 0) #endif diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 861b5ba76b..f612fda9cc 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -153,6 +153,8 @@ static const struct reg_script pch_misc_init_script[] = { #if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), #endif + /* Enable CLKRUN_EN for power gating LPC */ + REG_PCI_OR8(PCCTL, (CLKRUN_EN)), REG_SCRIPT_END }; |