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authorFurquan Shaikh <furquan@chromium.org>2017-08-04 15:58:26 -0700
committerFurquan Shaikh <furquan@google.com>2017-08-10 16:24:57 +0000
commit3406dd64c328bf0f2f1902d42b239f84c136e4f0 (patch)
tree3a041bafb43a260432cb0c9e2f769e5b177ad9fe /src/soc/intel/skylake
parent836f94c6126b8a9529321c6af71babdae3202592 (diff)
soc/intel/common/uart: Refactor uart_common_init
1. Create a new function uart_lpss_init which takes the UART LPSS controller out of reset and initializes and enables clock. 2. Instead of passing in m/n clock divider values as parameters to uart_common_init, introduce Kconfig variables so that uart_lpss_init can use the values directly without having to query the SoC. BUG=b:64030366 TEST=Verified that UART still works on APL and KBL boards. Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/Kconfig9
-rw-r--r--src/soc/intel/skylake/bootblock/uart.c6
2 files changed, 10 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 32c2654c4d..f0402a9e2b 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -317,4 +317,13 @@ config CPU_BCLK_MHZ
int
default 100
+# Clock divider parameters for 115200 baud rate
+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
+ hex
+ default 0x30
+
+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
+ hex
+ default 0xc35
+
endif
diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c
index 26b81c0589..b7ab241f77 100644
--- a/src/soc/intel/skylake/bootblock/uart.c
+++ b/src/soc/intel/skylake/bootblock/uart.c
@@ -31,10 +31,6 @@
#define PCR_SIO_PCH_LEGACY_UART1 (1 << 1)
#define PCR_SIO_PCH_LEGACY_UART2 (1 << 2)
-/* Clock divider parameters for 115200 baud rate */
-#define CLK_M_VAL 0x30
-#define CLK_N_VAL 0xc35
-
/* UART2 pad configuration. Support RXD and TXD for now. */
static const struct pad_config uart2_pads[] = {
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
@@ -45,7 +41,7 @@ void pch_uart_init(void)
{
uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
- uart_common_init(PCH_DEV_UART2, base, CLK_M_VAL, CLK_N_VAL);
+ uart_common_init(PCH_DEV_UART2, base);
/* Put UART2 in byte access mode for 16550 compatibility */
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))