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| author | Jingle Hsu <jingle_hsu@wiwynn.com> | 2020-11-03 20:40:08 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-11 07:35:13 +0000 |
| commit | 32d0549a6b8f6030428ea9399209fcfbaad2670c (patch) | |
| tree | 768bd40962727fc4088f553954b9aa060d050a2b /src/soc/intel/skylake | |
| parent | 7ed4039703552b4f7d6165cc1e895ca8c6d280e0 (diff) | |
mb/ocp/deltalake: Update GPIO configurations according to schematics
On Delta Lake DVT, dump GPIO settings from UEFI firmware for new PCH
(C621A) by util/inteltool and generate the header file by util/intelp2m.
The DVT and EVT GPIO configurations are the same.
The initial value of GPP_B20 (POST complete) should be high, otherwise
BIC would get incorrect sensor readings and see events like PCH prochot.
Tested=On OCP Delta Lake DVT, dump GPIO configurations
by Intel ITP and verify the results match with the header file.
Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47229
Reviewed-by: Tim Chu <Tim.Chu@quantatw.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
0 files changed, 0 insertions, 0 deletions