diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-11-25 11:57:28 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-11-26 11:55:10 +0000 |
| commit | 24ab1c5db6a48f27d1541f8f356127a14111358e (patch) | |
| tree | c063631796d2955bd3821802fb2cf457b12e6574 /src/soc/intel/skylake | |
| parent | 0d2dbcab5f08329567c2acbf54bcb7bd9ad5a8f6 (diff) | |
soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T
It is a requirement for Firmware to have Firmware Interface Table (FIT),
which contains pointers to each microcode update.
The microcode update is loaded for all logical processors before reset vector.
FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are
input parameters to TempRamInit API.
If these values are 0, FSP will not attempt to update microcode.
Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place
hence skipping FSP-T loading ucode after CPU reset options.
Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and
CONFIG_CPU_MICROCODE_CBFS_LEN
Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/fspcar.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c index a4c3726492..0d27f57698 100644 --- a/src/soc/intel/skylake/fspcar.c +++ b/src/soc/intel/skylake/fspcar.c @@ -23,10 +23,19 @@ const FSPT_UPD temp_ram_init_params = { .Reserved = {0}, }, .FsptCoreUpd = { - .MicrocodeRegionBase = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, - .MicrocodeRegionSize = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, + /* + * It is a requirement for firmware to have Firmware Interface Table + * (FIT), which contains pointers to each microcode update. + * The microcode update is loaded for all logical processors before + * cpu reset vector. + * + * All SoC since Gen-4 has above mechanism in place to load microcode + * even before hitting CPU reset vector. Hence skipping FSP-T loading + * microcode after CPU reset by passing '0' value to + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + */ + .MicrocodeRegionBase = 0, + .MicrocodeRegionLength = 0, .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, |