diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-12-18 10:24:55 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-07 10:27:32 +0000 |
| commit | f212cf3506a9ad3d699a4afe148bfd554932f7b8 (patch) | |
| tree | 86f810f53d78c9f1e368f4e75d3991158cec2fcf /src/soc/intel/skylake | |
| parent | 844eda0f3b69e8b724fdf14fc663f808f686037f (diff) | |
soc/intel: Standardize names of common MSRs
Use defined name in Intel 64 and IA-32 Architectures Software
Developer’s Manual.
Renamed MSRs are (register address, register name):
0x35 MSR_CORE_THREAD_COUNT
0x121 MSR_EMULATE_PM_TIMER
0x1f4 MSR_PRMRR_PHYS_BASE
0x1f5 MSR_PRMRR_PHYS_MASK
0x2f4 MSR_UNCORE_PRMRR_PHYS_BASE
0x2f5 MSR_UNCORE_PRMRR_PHYS_MASK
Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5c5d8a94d9..0f0518aeaf 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -420,7 +420,7 @@ static void enable_pm_timer_emulation(void) /* Set PM1 timer IO port and enable*/ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TMR, msr); + wrmsr(MSR_EMULATE_PM_TIMER, msr); } /* All CPUs including BSP will run the following function. */ @@ -528,7 +528,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) * be reloaded after the core PRMRR MSRs are programmed. */ msr1 = rdmsr(MTRR_CAP_MSR); - msr2 = rdmsr(PRMRR_PHYS_BASE_MSR); + msr2 = rdmsr(MSR_PRMRR_PHYS_BASE); if (msr2.lo && (current_patch_id == new_patch_id - 1)) return 0; else |