diff options
| author | Eugene Myers <edmyers@tycho.nsa.gov> | 2020-01-21 16:46:16 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-04 18:54:01 +0000 |
| commit | ebc8423cbcb0bcd95c45e68cdf04af9f10be1bfe (patch) | |
| tree | 1bdfad8f25beaed979639b5e2f0b302d84f99045 /src/soc/intel/skylake | |
| parent | c9ac0bcb9827ab2bef5fd7548eb13302cfd9c57d (diff) | |
soc/intel: Add get_pmbase
Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure
that the pmbase is accessable by the SMI handler during runtime.
The pmbase has to be accounted for in the BIOS resource list so
that the SMI handler is allowed this access.
Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pm.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/pmutil.c | 6 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 18b0c15d64..007d29cadc 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -197,4 +197,7 @@ static inline int deep_s5_enabled(void) return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS)); } +/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 2b2141b377..afe9b71117 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -275,3 +275,9 @@ void soc_fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return ACPI_BASE_ADDRESS; +} |