diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-11-22 20:00:28 -0800 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-29 17:18:02 +0000 |
| commit | d149bfa17fb1fca7e0a388fd6c0cbb088069d0d5 (patch) | |
| tree | 6b66aaea3729afbe3ae95138c4bda91e1a767a18 /src/soc/intel/skylake | |
| parent | 95ee5996f70c67c926e907d37f8f1f040fbcb3a6 (diff) | |
soc/intel: Configure P2SB before other PCH controllers
This change updates bootblock_pch_early_init() to perform P2SB
configuration before any other PCH controllers are initialized. This
is done because the other controllers might perform PCR settings which
requires the PCR base address to be configured. As the PCR base
address configuration happens during P2SB initialization, this change
moves the p2sb init calls before any other PCH controller
initialization.
BUG=b:171534504
Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47885
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c6b2ad966a..38ae916dad 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -29,9 +29,14 @@ void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + + fast_spi_early_init(SPI_BASE_ADDRESS); } static void soc_config_acpibase(void) |