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authorElyes HAOUAS <ehaouas@noos.fr>2019-03-21 15:38:06 +0100
committerNico Huber <nico.h@gmx.de>2019-04-26 16:49:13 +0000
commitc3385070d6e86dbde71dddbdef94ffa5579f9d11 (patch)
treee2d65c2c0550b67092d008ca31c3c22e11b932f0 /src/soc/intel/skylake
parent9df72e0471296d9bc2981646490c1f8b5b1e54e0 (diff)
soc/{amd,intel}/chip: Use local include for chip.h
Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/acpi.c3
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c3
-rw-r--r--src/soc/intel/skylake/chip.c3
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c3
-rw-r--r--src/soc/intel/skylake/cpu.c3
-rw-r--r--src/soc/intel/skylake/finalize.c3
-rw-r--r--src/soc/intel/skylake/include/fsp11/soc/ramstage.h3
-rw-r--r--src/soc/intel/skylake/include/fsp20/soc/ramstage.h3
-rw-r--r--src/soc/intel/skylake/memmap.c3
-rw-r--r--src/soc/intel/skylake/pei_data.c3
-rw-r--r--src/soc/intel/skylake/pmc.c3
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c3
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c3
-rw-r--r--src/soc/intel/skylake/thermal.c3
14 files changed, 28 insertions, 14 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 26a131ddc2..bd944dac16 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -21,7 +21,6 @@
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <cbmem.h>
-#include <chip.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/msr.h>
@@ -51,6 +50,8 @@
#include <wrdd.h>
#include <device/pci_ops.h>
+#include "chip.h"
+
/*
* List of suported C-states in this processor.
*/
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 0f6c8a85d4..c95a8d80e8 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
#include <device/pci_ops.h>
-#include <chip.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <intelblocks/cse.h>
@@ -37,6 +36,8 @@
#include <soc/pmc.h>
#include <soc/smbus.h>
+#include "../chip.h"
+
#define PCR_DMI_DMICTL 0x2234
#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
#define PCR_DMI_ACPIBA 0x27B4
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 9094348e78..6f90178f52 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -15,7 +15,6 @@
*/
#include <arch/acpi.h>
-#include <chip.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -33,6 +32,8 @@
#include <soc/ramstage.h>
#include <string.h>
+#include "chip.h"
+
void soc_init_pre_device(void *chip_info)
{
/* Snapshot the current GPIO IRQ polarities. FSP is setting a
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index c16a913218..d179598699 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <chip.h>
#include <bootmode.h>
#include <bootstate.h>
#include <device/pci.h>
@@ -42,6 +41,8 @@
#include <soc/systemagent.h>
#include <string.h>
+#include "chip.h"
+
struct pcie_entry {
unsigned int devfn;
unsigned int func_count;
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 47d484162d..52b0e194e6 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -20,7 +20,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <chip.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
@@ -46,6 +45,8 @@
#include <soc/systemagent.h>
#include <timer.h>
+#include "chip.h"
+
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
static const u8 power_limit_time_sec_to_msr[] = {
[0] = 0x00,
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index c69dffbe41..5d7e1e0034 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -18,7 +18,6 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <bootstate.h>
-#include <chip.h>
#include <console/console.h>
#include <console/post_codes.h>
#include <cpu/x86/mp.h>
@@ -41,6 +40,8 @@
#include <stdlib.h>
#include <timer.h>
+#include "chip.h"
+
#define PSF_BASE_ADDRESS 0xA00
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
index 3ab0efa7e5..2071d58b49 100644
--- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
@@ -17,11 +17,12 @@
#ifndef _SOC_RAMSTAGE_H_
#define _SOC_RAMSTAGE_H_
-#include <chip.h>
#include <device/device.h>
#include <fsp/ramstage.h>
#include <fsp/soc_binding.h>
+#include "../../../chip.h"
+
#define FSP_SIL_UPD SILICON_INIT_UPD
#define FSP_MEM_UPD MEMORY_INIT_UPD
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
index e75b350049..e5660a6f66 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -17,11 +17,12 @@
#ifndef _SOC_RAMSTAGE_H_
#define _SOC_RAMSTAGE_H_
-#include <chip.h>
#include <device/device.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include "../../../chip.h"
+
#define FSP_SIL_UPD FSP_S_CONFIG
#define FSP_MEM_UPD FSP_M_CONFIG
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 60a7070408..fde916a922 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -17,7 +17,6 @@
#include <arch/ebda.h>
#include <device/mmio.h>
#include <cbmem.h>
-#include <chip.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -29,6 +28,8 @@
#include <soc/systemagent.h>
#include <stdlib.h>
+#include "chip.h"
+
size_t mmap_region_granularity(void)
{
if (CONFIG(HAVE_SMI_HANDLER))
diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c
index a2887ac4c4..203a1d8e36 100644
--- a/src/soc/intel/skylake/pei_data.c
+++ b/src/soc/intel/skylake/pei_data.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <chip.h>
#include <console/streams.h>
#include <device/device.h>
#include <device/pci_def.h>
@@ -25,6 +24,8 @@
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
+#include "chip.h"
+
static void ABI_X86 send_to_console(unsigned char b)
{
console_tx_byte(b);
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index 5ff05c26c2..01def44b06 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -16,7 +16,6 @@
*/
#include <bootstate.h>
-#include <chip.h>
#include <console/console.h>
#include <device/mmio.h>
#include <device/device.h>
@@ -28,6 +27,8 @@
#include <soc/pci_devs.h>
#include <soc/pm.h>
+#include "chip.h"
+
void pmc_set_disb(void)
{
/* Set the DISB after DRAM init */
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index d8188f6924..0501b04493 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -17,7 +17,6 @@
#include <arch/cbfs.h>
#include <arch/early_variables.h>
#include <assert.h>
-#include <chip.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <device/device.h>
@@ -37,6 +36,8 @@
#include <stdint.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include "../chip.h"
+
/* SOC initialization before RAM is enabled */
void soc_pre_ram_init(struct romstage_params *params)
{
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index dcfc3632ca..1e81d7aa05 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -20,7 +20,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cbmem.h>
-#include <chip.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <fsp/util.h>
@@ -37,6 +36,8 @@
#include <timestamp.h>
#include <security/vboot/vboot_common.h>
+#include "../chip.h"
+
#define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \
0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
diff --git a/src/soc/intel/skylake/thermal.c b/src/soc/intel/skylake/thermal.c
index 711b714b04..97cd1b7779 100644
--- a/src/soc/intel/skylake/thermal.c
+++ b/src/soc/intel/skylake/thermal.c
@@ -15,7 +15,6 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
-#include <chip.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -23,6 +22,8 @@
#include <soc/pci_devs.h>
#include <soc/thermal.h>
+#include "chip.h"
+
#define MAX_TRIP_TEMP 205
#define DEFAULT_TRIP_TEMP 50