soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper

This patch ensures coreboot is not publishing above 4GB mmio resource
if soc common config "enable_above_4GB_mmio" not enable.

Publishing unnecessary 4GB above MMIO resource with wrong base and size
is causing problem while working with discrete GPU.

Unable to boot with dGPU on IA platform with below error:

[    2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[    2.302858] pcieport 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
[    2.309427] pcieport 0000:00:1c.0:   bridge window [mem 0xb2000000-0xb20fffff]
[    2.316679] pcieport 0000:00:1c.0:   bridge window [mem 0x840000000-0x8c01fffff 64bit pref]
[    2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[    2.330502] pcieport 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
[    2.337062] pcieport 0000:00:1c.0:   bridge window [mem 0xb2000000-0xb20fffff]
[    2.344317] pcieport 0000:00:1c.0:   bridge window [mem 0xa0000000-0xb01fffff 64bit pref]
[    2.352541] [drm] Not enough PCI address space for a large BAR.

Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>

5 files changed, 28 insertions, 21 deletions

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 332f797dbb..bf54854425 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2009 coresystems GmbH
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2019 Intel Corporation.
+ * Copyright (C) 2015-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -207,6 +207,9 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 
 	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
 		sgx_fill_gnvs(gnvs);
+
+	/* Fill in Above 4GB MMIO resource */
+	sa_fill_gnvs(gnvs);
 }
 
 unsigned long acpi_fill_mcfg(unsigned long current)
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index c4544e8a6e..b2467f9918 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2007-2009 coresystems GmbH
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -70,6 +70,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	EPCS,	8,	// 0x43 - SGX Enabled status
 	EMNA,	64,	// 0x44 - 0x4B EPC base address
 	ELNG,	64,	// 0x4C - 0x53 EPC Length
+	E4GM,	8,	// 0x54 - Enable above 4GB MMIO Resource
+	A4GB,	64,	// 0x55 - 0x5C Base of above 4GB MMIO Resource
+	A4GS,	64,	// 0x5D - 0x64 Length of above 4GB MMIO Resource
 
 	/* IGD OpRegion */
 	Offset (0xb4),
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index 589fcc1518..89380aa194 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2007-2009 coresystems GmbH
  * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,9 +17,6 @@
 
 #include <soc/iomap.h>
 
-#define BASE_32GB	0x800000000
-#define SIZE_16GB	0x400000000
-
 Name (_HID, EISAID ("PNP0A08"))	/* PCIe */
 Name (_CID, EISAID ("PNP0A03"))	/* PCI */
 
@@ -214,20 +211,18 @@ Method (_CRS, 0, Serialized)
 	Add (Subtract (PMAX, PMIN), 1, PLEN)
 
 	/* Patch PM02 range based on Memory Size */
-	CreateQwordField (MCRS, PM02._MIN, MMIN)
-	CreateQwordField (MCRS, PM02._MAX, MMAX)
-	CreateQwordField (MCRS, PM02._LEN, MLEN)
-
-	Store (\_SB.PCI0.MCHC.TUUD, Local0)
-
-	If (LLessEqual (Local0, BASE_32GB)) {
-		Store (BASE_32GB, MMIN)
-		Store (SIZE_16GB, MLEN)
+	If (LEqual (A4GS, 0)) {
+		CreateQwordField (MCRS, PM02._LEN, MSEN)
+		Store (0, MSEN)
 	} Else {
-		Store (0, MMIN)
-		Store (0, MLEN)
+		CreateQwordField (MCRS, PM02._MIN, MMIN)
+		CreateQwordField (MCRS, PM02._MAX, MMAX)
+		CreateQwordField (MCRS, PM02._LEN, MLEN)
+		/* Set 64bit MMIO resource base and length */
+		Store (A4GS, MLEN)
+		Store (A4GB, MMIN)
+		Subtract (Add (MMIN, MLEN), 1, MMAX)
 	}
-	Subtract (Add (MMIN, MLEN), 1, MMAX)
 
 	Return (MCRS)
 }
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index 814dd949d0..b447d79958 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -75,6 +75,9 @@
 #define PTT_TXT_BASE_ADDRESS	0xfed30800
 #define PTT_PRESENT		0x00070000
 
+#define ABOVE_4GB_MEM_BASE_ADDRESS	(128ULL * GiB)
+#define ABOVE_4GB_MEM_BASE_SIZE	(64ULL * GiB)
+
 /*
  * I/O port address space
  */
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 72b1ac99d3..d5f62f63fc 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2008-2009 coresystems GmbH
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -60,7 +60,10 @@ typedef struct global_nvs_t {
 	u8	ecps; /* 0x43 - SGX Enabled status */
 	u64	emna; /* 0x44 - 0x4B EPC base address */
 	u64	elng; /* 0x4C - 0x53 EPC Length */
-	u8	rsvd[96];
+	u8	e4gm; /* 0x54 - Enable above 4GB MMIO Resource */
+	u64	a4gb; /* 0x55 - 0x5C Base of above 4GB MMIO Resource */
+	u64	a4gs; /* 0x5D - 0x64 Length of above 4GB MMIO Resource */
+	u8	rsvd[79];
 
 	/* IGD OpRegion */
 	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */