nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings

There are multiple different devicetree setting formats for graphics
panel settings present in coreboot. Replace the ones for the platforms
that already have (mostly) unified gma/graphics setup code by a unified
struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt
the devicetrees accordingly.

Always ensure that values don't overflow by applying appropriate masks.

The remaining platforms implementing panel settings (GM45, i945, ILK and
SNB) can be migrated later after unifying their gma/graphics setup code.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

2 files changed, 15 insertions, 24 deletions

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 7d9d93460c..027a2e29e4 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -6,7 +6,7 @@
 #include <acpi/acpi_device.h>
 #include <device/i2c_simple.h>
 #include <drivers/i2c/designware/dw_i2c.h>
-#include <drivers/intel/gma/i915.h>
+#include <drivers/intel/gma/gma.h>
 #include <intelblocks/cfg.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -37,16 +37,7 @@ struct soc_intel_skylake_config {
 	struct soc_power_limits_config power_limits_config;
 
 	/* IGD panel configuration */
-	unsigned int gpu_pp_up_delay_ms;
-	unsigned int gpu_pp_down_delay_ms;
-	unsigned int gpu_pp_cycle_delay_ms;
-	unsigned int gpu_pp_backlight_on_delay_ms;
-	unsigned int gpu_pp_backlight_off_delay_ms;
-	unsigned int gpu_pch_backlight_pwm_hz;
-	enum {
-		GPU_BACKLIGHT_POLARITY_HIGH = 0,
-		GPU_BACKLIGHT_POLARITY_LOW,
-	} gpu_pch_backlight_polarity;
+	struct i915_gpu_panel_config panel_cfg;
 
 	/* Gpio group routed to each dword of the GPE0 block. Values are
 	 * of the form GPP_[A:G] or GPD. */
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index 46dc9dbfab..d41c4aa644 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -15,6 +15,7 @@
 void graphics_soc_panel_init(struct device *dev)
 {
 	struct soc_intel_skylake_config *conf = config_of(dev);
+	const struct i915_gpu_panel_config *panel_cfg;
 	struct resource *mmio_res;
 	uint8_t *base;
 	u32 reg32;
@@ -22,27 +23,29 @@ void graphics_soc_panel_init(struct device *dev)
 	if (!conf)
 		return;
 
+	panel_cfg = &conf->panel_cfg;
+
 	mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!mmio_res || !mmio_res->base)
 		return;
 	base = (void *)(uintptr_t)mmio_res->base;
 
-	reg32 = conf->gpu_pp_up_delay_ms * 10 << 16;
-	reg32 |= conf->gpu_pp_backlight_on_delay_ms * 10;
+	reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
+	reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
 	write32(base + PCH_PP_ON_DELAYS, reg32);
 
-	reg32 = conf->gpu_pp_down_delay_ms * 10 << 16;
-	reg32 |= conf->gpu_pp_backlight_off_delay_ms * 10;
+	reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
+	reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
 	write32(base + PCH_PP_OFF_DELAYS, reg32);
 
 	reg32 = read32(base + PCH_PP_DIVISOR);
 	reg32 &= ~0x1f;
-	reg32 |= (DIV_ROUND_UP(conf->gpu_pp_cycle_delay_ms, 100) + 1) & 0x1f;
+	reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f;
 	write32(base + PCH_PP_DIVISOR, reg32);
 
 	/* So far all devices seem to use the PCH PWM function.
 	   The CPU PWM registers are all zero after reset.      */
-	if (conf->gpu_pch_backlight_pwm_hz) {
+	if (panel_cfg->backlight_pwm_hz) {
 		/* Reference clock is 24MHz. We can choose either a 16
 		   or a 128 step increment. Use 16 if we would have less
 		   than 100 steps otherwise. */
@@ -51,7 +54,7 @@ void graphics_soc_panel_init(struct device *dev)
 		u32 south_chicken1;
 
 		south_chicken1 = read32(base + SOUTH_CHICKEN1);
-		if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
+		if (panel_cfg->backlight_pwm_hz > hz_limit) {
 			pwm_increment = 16;
 			south_chicken1 &= ~1;
 		} else {
@@ -60,15 +63,12 @@ void graphics_soc_panel_init(struct device *dev)
 		}
 		write32(base + SOUTH_CHICKEN1, south_chicken1);
 
-		pwm_period = 24 * 1000 * 1000 / pwm_increment
-				/ conf->gpu_pch_backlight_pwm_hz;
+		pwm_period = 24 * 1000 * 1000 / pwm_increment / panel_cfg->backlight_pwm_hz;
 		/* Start with a 50% duty cycle. */
-		write32(base + BLC_PWM_PCH_CTL2,
-			pwm_period << 16 | pwm_period / 2);
+		write32(base + BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
 
 		write32(base + BLC_PWM_PCH_CTL1,
-			!!conf->gpu_pch_backlight_polarity << 29 |
-			BLM_PCH_PWM_ENABLE);
+			!!panel_cfg->backlight_polarity << 29 | BLM_PCH_PWM_ENABLE);
 	}
 }