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authorAngel Pons <th3fanbus@gmail.com>2020-12-11 17:00:42 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-12-14 10:40:44 +0000
commit950cdbc3e25f021cb71693fb7c27b0588da1233d (patch)
tree1dfac983484151ff90782ef435de1336f65d6815 /src/soc/intel/skylake
parent124e9f293bd4918e2125456dad8821bfa0fdb491 (diff)
soc/intel/skylake: Drop always-zero PowerLimit4 dt setting
Unset devicetree settings default to zero, so the devicetree setting can be removed. Looks like no one needs it anyway. Change-Id: Iad94538c5465347b37a99c6c9f20988168661593 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/chip.c2
-rw-r--r--src/soc/intel/skylake/chip.h3
2 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 3eb72fa57a..c9519cdc29 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -303,7 +303,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
- tconfig->PowerLimit4 = config->PowerLimit4;
+ tconfig->PowerLimit4 = 0;
/*
* To disable HECI, the Psf needs to be left unlocked
* by FSP till end of post sequence. Based on the devicetree
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 67739a4532..4d92410b65 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -87,9 +87,6 @@ struct soc_intel_skylake_config {
/* TCC activation offset */
uint32_t tcc_offset;
- /* Package PL4 power limit in Watts */
- u32 PowerLimit4;
-
/* Whether to ignore VT-d support of the SKU */
int ignore_vtd;