diff options
author | Subrata Banik <subrata.banik@intel.com> | 2019-07-08 14:49:22 +0530 |
---|---|---|
committer | Subrata Banik <subrata.banik@intel.com> | 2019-07-11 05:57:41 +0000 |
commit | 10a9432cc2ad77234442bd639194c5a80050854e (patch) | |
tree | ce6f68feab9582d2ab62765cd0d9a3262bb62b69 /src/soc/intel/skylake | |
parent | 5b9948140f97eceb47ba026d7bad6dfa2a3c483d (diff) |
soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer
for better code sharing. Also ported CB:33512 for SPT and ICP PCH.
Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r-- | src/soc/intel/skylake/chip.c | 3 | ||||
-rw-r--r-- | src/soc/intel/skylake/chip.h | 3 | ||||
-rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 3 | ||||
-rw-r--r-- | src/soc/intel/skylake/lpc.c | 11 |
4 files changed, 6 insertions, 14 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 7f28340ba4..7fbe9e519c 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -237,6 +237,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->SlowSlewRateForSa = config->SlowSlewRateForSa; params->FastPkgCRampDisable = config->FastPkgCRampDisable; + /* Legacy 8254 timer support */ + params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; + soc_irq_settings(params); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 9c8e2bfaa9..da941dc643 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -513,9 +513,6 @@ struct soc_intel_skylake_config { /* Enable/Disable host reads to PMC XRAM registers */ u8 PchPmPmcReadDisable; - /* Statically clock gate 8254 PIT. */ - u8 clock_gate_8254; - /* * Use SD card detect GPIO with default config: * - Edge triggered diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 08f5d79349..a1fced293d 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -315,6 +315,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + /* Legacy 8254 timer support */ + params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER; + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 8d6228c096..d8e5ccc6c0 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -96,16 +96,6 @@ static const struct reg_script pch_misc_init_script[] = { REG_SCRIPT_END }; -static void clock_gate_8254(struct device *dev) -{ - const config_t *config = dev->chip_info; - - if (!config->clock_gate_8254) - return; - - itss_clock_gate_8254(); -} - void lpc_soc_init(struct device *dev) { const config_t *const config = dev->chip_info; @@ -125,5 +115,4 @@ void lpc_soc_init(struct device *dev) soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); - clock_gate_8254(dev); } |